Skip to main content

Full text of "Burr Brown Collection Of Applications Bulletins OCR"

See other formats


Burr-Brown 

Collection of 

Applications 

Bulletins 



BURR - BROWN® 



TABLE OF CONTENTS 



SECTION 1, Burr-Brown Technical Literature 

Thermal and electrical properties of selected packaging materials 

Implementation and applications of current sources and current receivers 

SECTION 2, Operational Amplifiers 

Classical op amp or current-feedback op amp? This composite op amp gives you the best of both worlds 33 

Feedback plots define op amp AC performance 35 

SECTION 3, Instrumentation Amplifiers 

Increasing INA1 17 differential input range 49 

AC-coupling instrumentation and difference amplifiers 51 

±200V difference amplifier with common-mode monitor 55 

Input overload protection for the RCV420 4-20mA current-loop receiver 57 

Extending the common-mode range of difference amplifiers 61 

Boost amplifier output swing with simple modification 67 

to 20mA receiver using RCV420 69 

Boost instrumentation amp CMR with common-mode driven supplies 71 

(excellent general IA tutorial) 

Input filtering the INA1 17 +200V difference amplifier 79 

(applies to input filtering of all IAs) 

4-20mA to 0-20mA converter and current summing current-to-current converters 83 

IC building blocks form complete isolated 4-20mA current-loop systems 87 

Single-supply, low-power measurements of bridge networks 97 

Diode-based temperature measurement 99 

SECTION 4, Isolation Products 

Single-supply operation of isolation amplifiers 105 

Boost ISO 120 bandwidth to more than 100kHz 109 

Synchronization of ISO120/121 isolation amplifiers 113 

Simple output filter eliminates iso amp output ripple and keeps full bandwidth 1 15 

Very low cost analog isolation with power 117 

SECTION 5, Voltage And Current References and Active Filters 

Make a precision current source or current sink 121 

Voltage reference filters 123 

Make a precision -10V reference 125 

Make a precision +10V reference 127 

Make a -10V to +10V adjustable precision voltage source 129 

Low power supply voltage operation of REF102 10V precision voltage reference 131 

Sallen-Key low-pass filter design program 1 33 

Fast settling low-pass filter 1 39 

A low noise, low distortion design for antialiasing and anti-imaging filters 143 

MFB low-pass filter design program 151 

Filter design program for the UAF42 universal active filter 159 

SECTION 9, Analog-To-Digital Converters 

Increasing ADC603 input range 173 

Using the ADS7800 12 bit ADC with unipolar input signals 175 

SECTION 10, Voltage-To-Frequency Converters 

Frequency-to- voltage conversion 177 



SECTION 11, High-Speed Data Converters 

High-speed data conversion 185 

SECTION 13, Heat-Sinking and TO-3 Mounting 

Heat sinking — TO-3 thermal model 227 

Mounting considerations for TO-3 packages • I •••• (•••>ll>t <•••>! ■(•(•(•(•■•■••OIMt ■••> • •!> Ali7 

SECTION 

Operational amplifier and instrumentation amplifier macromodels 237 



CONTENTS BY AB-NUMBER 



AB-001 


49 


AB-021 


113 


AB-002 


121 


AB-022 


139 


AB-003 


123 


AB-023 


115 


AB-004 


125 


AB-024 


117 


AB-005 


127 


AB-025 


71 


AB-006 


129 


AB-026 


143 


AB-007 


33 


AB-027 


185 


AB-008 


51 


AB-028 


35 


AB-009 


105 


AB-029 


79 


AB-010 


55 


AB-030 


1 


AB-011 


131 


AB-031 


83 


AB-012 


109 


AB-032 


87 


AB-013 


173 


AB-033 


97 


AB-014 


57 


AB-034 


151 


AB-015 


61 


AB-035 


159 


AB-016 


67 


AB-036 


99 


AB-017 


133 


AB-037 


229 


AB-018 


69 


AB-038 


227 


AB-019 


175 


AB-039 


FUTURE 


AB-020 


237 


AB-040 


177 



SELECTED PACKAGING MATERIALS 



©7997 Burr-Brown Corp. 



MATERIAL 


THERMAL CONDUCTIVITY 

(W/ln-°C) 


THERMAL EXPANSION 

(10-ty'C) 


TCR 

(10-«/°C) 


RESISTIVITY 

at mop 
A 1 ZD U 

(na-cm) 


NOM 


LOW 


HIGH 


NOM 


LOW 


HIGH 


ALUMINUM 


6.02 


5.63 


6.38 


23.9 


19.4 


25 


4290 


2.66 


ANTIMONY 


0.620 


0.481 


0.648'W 




8.46 


10.8 




41.7 


ARSENIC 


1.28 


1.08"" 


1.37<» 


4.7 








33.3 


BARIUM 


0.468 






18 








50.0 


BERYLLIUM 


5.10 


4.04 


5.54<M 


12 






25000 


5.9 


BISMUTH 


0.201"" 


0.134' a > 


0.233"" 


13 








106.8 


BORON 


0.696 


0.478"" 


0.808'W 


8.3 








1.8 x 10 ,2 < m ) 


CADMIUM 


2.46"" 


2.1110' 


2.62"" 


29.9 






4200 


6.83 


CALCIUM 


5.10 


3.20 


5.23 


22 






4160 


3.43 


CARBON 


3.70"" 


0.0404(i> 


58.9< z| 




0.54 


4.32 




1375") 


CESIUM 


0.912 






97 








20.0 


CHROMIUM'*' 


2.38 






6.1 






3000 


13.0 


COBALT' 1 " 


2.54 






12 






6040 


6.24 


COPPER 


10.2 






17 






6800 


1.673 


GALLIUM 


1.04W 


0.404<o> 


2.24") 


18 








56.8 


GERMANIUM 


1.53 


1.18"" 


1.69'W 


5.9 








10 2 - 10 7 <» 


GOLD (10.2 oz. troy/in 3 ) 


8.08 






14.2 






4000 


2.19 


HAFNIUM 


0.584 


0.569"" 


0.592»> 


5.9 






3800 


32.4 


INDIUM"" 


2.08 


1.94"" 


2.1210) 


32 








8.37 


IRIDIUM 


3.73 






6.8 






3925 


5.3 


IRON 


2.04 


1.85"" 


2.20<M 


11.7 






6510 


9.71 


LEAD 


0.897 


0.874"" 


0.904»> 


29.3 






3360 


20.65 


MAGNESIUM' 1 " 


3.96 






25 






16500 


4.46 


MANGANESE 


0.198 






22 








185 


MOLYBDENUM 


3.50 






5.4 








5.17 


NICKEL 


2.31 


2. 10"* 


2.39(f) 


13 






6900 


6.84 


NIOBIUM 


1.36 






7.1 








12.5 


OSMIUM' 1 " 


1.55 






4.7 






4200 


9.5 


PALLADIUM 


1.82 






11.9 






3770 


10.8 


PHOSPHORUS 




.006411 


.307"" 


126 








10 17 


PLATINUM 


1.82 






8.8 






3927 


9.83 


RHENIUM" 


1.22 






6.7 






3950 


19.3 


RHODIUM 


3.81 






8.3 






4200 


4.51 


RUBIDIUM 


1.48 






90 








12.5 


RUTHENIUM 


2.97 






9.6 








7.6") 


SELENIUM 


0.033' d > 


0.01 3<8 


0.115'a) 


38 








12'*°) 


SILICON 


3.78 


2.1 


4.27«» 


3511KAB) 


2.9 


7.4 




lOMolO 8 ") 


SILVER 


10.9 






19.6 






4100 


1.59 


STRONTIUM 


0.899 


0.826"" 


0.924») 










23.0 


SULFUR' 1 " 


0.0069 


0.0039"" 


0.0073'K 


65 








2X10 23 "") 



C/> 
H 
Z 
HI 

LU 
—I 
LU 



NOTES: Values at 20°C unless otherwise specified, (a) At 1 00°C. (p) At 0°C. (a) || to triangle axis, (b) ± to triangle axis, (c) Average value; graphite varies from 2.0 to 
5.6 depending on type and orientation. Pyrolytic graphite is 0.16 and 50 X and || to layer planes, (d) Crystalline, 1 to c-axis; polycrystalline = 0.006W/in-°C. (e) || to a- 
axis. (f) || to b-axis. (g) || to c-axis. (h) Armco iron, (i) White phosphorous, (j) Amorphous, (k) Polycrystalline. (I) Resistivity at 0°C. (m) Intrinsic value, actual value sensitive 
to purity, (t) With 1 O^/cm 3 to 1 14 /cm 3 impurity concentration, (z) Type Ha diamond. (AB) Measured by J. Naylor. (AC) Crystalline, amorphous » 1 6 un-cm. 



®199l Burr-Brown Corporation 



AB-030 



Printed in U.S.A. April, 1991 



THERMAL AND ELECTRICAL PROPERTIES OF SELECTED PACKAGING MATERIALS (CONT) 







THERMAL CONDUCTIVITY 

(W/in-X) 


THERMAL EXPANSION 

(10-VC) 


TCR 


RESISTIVITY 
AT 20°C 




MATERIAL 


NOM 


LOW 


HIGH 


NOM 


LOW 


HIGH 


[10-«/°C] 


[nH-cm] 




TANTALUM 


1.46 






6.5 






3830 


12.4 


Sll 


TELLURIUM 


0.150 






17 








2x 10 5 


TIN 


1.701") 


1.3110) 


1.89< d ) 


23 


20 


25 


4700 


11.5 


z 

LU 


TITANIUM^ 


0.556 


0.5261°) 


0.569»> 


8.5 








47.8 


2 


TUNGSTEN 


4.39 


4.14 


4.50 


4.3 


4.2 


4.5 


5240 


5.6 


LU 
_l 


VANADIUM 


0.780 






7.7 








24.8-26.0 


UJ 


ZINC< k ' 


2.95 








17 


40 


4190 


5.8 




ZIRCONIUM 


0.576 


0.554 


0.589 


5.6 






4400 


41.0 




EPOXIES 




0.0042 


0.035 




11.0 


60 




10 21(m) 




GLASS-EPOXY(PC-GIO) 


0.08 






(n) 


10< n > 


151") 




10 21(m) 


O 


KAPTON 


0.0039 








34 


40 




1 n 2 ^) 


GAN 


NYLON 




0.0054 


0.0085 




82.8 


128 




1 2 <X"» 


PARYLENE 


0.0032 








35 


69 




10 22(m) 


OR 


RTV 


0.0053 


0.004 


0.008 


930 








3x10 15 < m > 


TEFLON 




0.0056 


0.0296 


83 


50 


162 




1()2«>n) 




MYLAR 




0.0045 


0.0073 




60 


95 




1021C") 




AIR 


0.00066 


















ALO, 


0.53M 


0.42'") 


0.85M 


6.7M 


6.5 


7.3 




5x 10 2 « m > 




BRASS*) 


2.95 








18 


21 


2000 


6.4 




BeO 


6.0 


5.5 


7.1 


8.0 


6.5 


8.7 




10 22,m > 


0) 
3 


EUTECTIC (Au-Si) MP 370°C 


5.5 






13.7 








2.53 


EUTECTIC (Au-Sn) MP 280°C 


6.4 






16 








2.6 


o 


EUTECTIC (Au-Ge) MP 356°C 


6.7 






12.6 








2.6 


LU 
Z 


FERRITE 


0.085 




0.159 




8 


12 




127 X 10 6 


< 


GLASS'*) 




0.010 


0.037 




0.55 


12.4 




lO^) 


-1 
_l 


KOVAR 


0.425 






5.5 








49.0 


SCE 


KOVAR-42 


0.28 






4.9 








78 


MANGANIN 


0.564 


0.523 


0.635 


18.7 






±15 


44 


m 


MICA 


0.011 


0.009 


0.017 




32.4 


48.6 




1()21(m) 




QUARTZ (Si0 2 ) 


0.035 


0.19»" d ) 


0.37<W°I 


0.55 








•|024<m> 




SAPPHIRE 


0.821 


0.691 


1.0 


6.67C) 


5.0W 


8.33< s > 








SOLDER (60/40) 


1.0 






23 








13.5 




STEEL (1008) 


1.2 






12 






6510 


11 




STEEL, STAINLESS 


0.35 303 


0.30 310 


094 50i 


18 304 






170 (AA) 


112^ 



NOTES: Values at 20°C unless otherwise specified, (a) At 1 00°C. (P) At 0°C. (d) J. to c-axis. (e) || to a-axis. (f) || to b-axis. (g) || to c-axis. (k) Polycrystalline. (m) Intrinsic 
value; actual value sensitive to purity, (n) 40-300 for vertical axis, (p) Yellow brass, (q) || to c-axis at 50°C. (r) X to c-axis at 50°C. (s) || to c-axis at 500°C. (v) 96%. (w) 
90%. (x) 99.5%. (y) See quartz. (AA) Nichrome 60% Ni, 25% Fe, 1 5% Cr. 



THERMAL CONDUCTIVITY (K) CONVERSIONS 



ORIGINAL UNIT 


CONVERSION UNIT 


EXAMPLE 

232 (BTU/hr-ft-°F) x 0.0440 
-10.2(watt/°C-in) 

FORMULAE 

•C/W r Len 9 th (in) 


cal 


watt 


watt 


BTU 


kg-cal 


watt 


s-cm-°C 


cm-°C 


in-°C 


hr-ft-°F 


hr-nVC 


m-°C 


1 cal/s-cm-°C 


1.0 


4.186 


10.63 


241.9 


360.0 


418.6 


1 watt/cm-°C 


0.2389 


1.0 


2.540 


57.8 


86.00 


100 


1 watt/in-°C 


0.09405 


0.3937 


1.0 


22.75 


33.86 


39.37 


1 BTU/hr-ft-°F 


4.1 34(1 0-*) 


0.01730 


0.0440 


1.0 


1.488 


1.730 


Area (in 2 ) • K (W/in-"C) 


1 kg-cal/hr-m-°C 


2.778(1 0- 3 ) 


0.01163 


0.0295 


0.672 


1.0 


1.163 


1 watt/m-°C 


0.002389 


0.01 


0.0254 


0.578 


0.8600 


1.0 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



I burr-brown APPLICATION GUIDE 
2| 31 Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S, Tucson Blvd. ■ Tucson, AZ 85705 

Tel: (602) 746-1111 • Twx: 910-952-111 ■ Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800)548-6132 

IMPLEMENTATION AND APPLICATIONS OF 
CURRENT SOURCES AND CURRENT RECEIVERS 



This application guide is intended as a source book for the 
design and application of: 

• Current sources 

• Current sinks 

• Floating current sources 

• Voltage-to-current converters 
(transconductance amplifiers) 

• Current-to-current converters (current mirrors) 

• Current-to-voltage converters 
(transimpedance amplifiers) 



CONTENTS 

DESIGN OF FIXED CURRENT SOURCES 

REF200 IC CURRENT SOURCE 

DESCRIPTION PIN STRAPPING REF200 FOR 50n.A— 400n.A ... 2 

RESISTOR PROGRAMMABLE CURRENT SOURCES 

AND SINKS USING REF200 AND ONE EXTERNAL OP AMP: 

Current Source or Sink With Compliance to 

Power Supply Rail and Current Out >100uA 4 

Current Source or Sink With Any Current Out 5 

Current Sources made with Voltage References 5 

Floating Current Source With Current Out >100uA 7 

Current Sources and Sinks and Current Mirrors 

Using an Amplifier and a Series Pass Element 7 

Floating Current Source With 

Current Out >100u.A and No Separate Power Supply 9 

CASCODING CURRENT SOURCES 
FOR IMPROVED OUTPUT IMPEDANCE, 
HIGH FREQUENCY PERFORMANCE, 
AND HIGH VOLTAGE COMPLIANCE: 



Cascoding with FETs 9 

200uA Floating Cascoded Current Source Using REF200..11 
300uA Floating Cascoded Current Source Using REF200..11 
400uA Floating Cascoded Current Source Using REF200..11 

NOISE REDUCTION OF CURRENT SOURCES 11 

APPLICATIONS OF FIXED CURRENT SOURCES 

VOLTAGE REFERENCES USING CURRENT SOURCES 12 

OP AMP OFFSET 

ADJUSTMENT USING 5mV REFERENCE 14 

WINDOW COMPARATOR USING 

FLOATING VOLTAGE REFERENCE 15 

RTD EXCITATION USING CURRENT REFERENCE 15 

DEAD BAND CIRCUITS USING CURRENT REFERENCE 16 



This is not an exhaustive collection of circuits, but a com- 
pendium of preferred ones. Where appropriate, suggested 
part numbers and component values are given. Where added 
components may be needed for stability, they are shown. 
Experienced designers may elect to omit these components 
in some applications, but less seasoned practitioners will be 
able to put together a working circuit free from the frustra- 
tion of how to make it stable. 

The applications shown are intended to inspire the imagina- 
tion of designers who will move beyond the scope of this 
work. 

R. Mark Stitt (602) 746-7445 



BIDIRECTIONAL CURRENT SOURCES 18 

LIMITING CIRCUITS USING 

BIDIRECTIONAL CURRENT SOURCES 18 

PRECISION TRIANGLE WAVEFORM GENERATOR 

USING BIDIRECTIONAL CURRENT SOURCES 19 

DUTY CYCLE MODULATOR USING 

BIDIRECTIONAL CURRENT SOURCES 19 

SLEW RATE LIMITER 20 

SINGLE SUPPLY INSTRUMENTATION AMPLIFIER 20 

VOLTAGE CONTROLLED CURRENT SOURCES 
VOLTAGE CONTROLLED 

CURRENT SOURCE USING INA105 20 

VOLTAGE CONTROLLED CURRENT SOURCE WITH 
INSTRUMENTATION AMPLIFIER INPUT— THE XTR101 22 

SINGLE SUPPLY VOLTAGE 

CONTROLLED CURRENT SOURCE— THE XTR110 22 

CURRENT-TO-VOLTAGE 

CONVERTERS, AND CURRENT RECEIVERS 

CURRENT RECEIVER WITH COMPLIANCE TO 

BOTH POWER SUPPLY RAILS USING THE INA105 24 

POWER AMP LOAD CURRENT 

MONITORING USING THE INA105 OR THE INA117 24 

4 to 20mA CURRENT LOOP RECEIVER 

WITH to 5V OUTPUT USES THE RCV420 25 

VIRTUAL GROUND CURRENT 

TO VOLTAGE CONVERTER 25 

PHOTODIODE AMPLIFIERS 26 

^3 L^5SS^V R Y ■■■iiHHiiMiiiii ■ 29 



1989 Burr-Brown Corporation AN-165A Printed in U.S.A. March, 1 990 



DESIGN OF FIXED 
CURRENT SOURCES 

REF200 IC CURRENT SOURCE DESCRIPTION 

The REF200 dual current source has two current sources 
plus a current mirror in an 8-pin plastic DIP (Figure 1). 
Because the circuit is fabricated with the Burr-Brown dielec- 
trically isolated Difet® Burr-Brown process, the three cir- 
cuit blocks are completely independent. No power supply 
connections are needed to the chip. Just apply 2.5V or more 
to a current source for a constant 100p:A output. Typical drift 
is less than 25ppm/°C and output impedance exceeds 500MQ. 



l A High 



Pin 1 



.High 

m 



I Source A 



)© © 



Substrate 



Mirror In 



I Source B 



Out 



Mirror 



Com 



I. Low 



LLow 



: — m 



Mirror Com Mirror Out 



FIGURE 1 . The REF200 Dual Current Source contains three 
completely independent circuit blocks — two 
IOOliA current sources, and a current mirror. 

The current mirror is useful in many applications. It uses a 
"full Wilson" type architecture as shown in Figure 2, with 
laser-trimming to ensure high accuracy. 




FIGURE 2. The REF200 Current Mirror uses a "full Wilson" 
architecture for high accuracy. 

Each of the two current sources are designed as shown in 
Figure 3. Zero temperature coefficient (TC) is achieved by 
combining positive TC currents with a negative TC current. 
The positive TC currents are generated by a bandgap cell. 



Current mirror Q - Q 2 forces equal currents to flow in 8/1 
emitter ratioed devices Q 7 and Q g . The proportional to 
absolute temperature (PTAT) voltage difference between 
the emitters — (k • t/q) • ln(8) — is forced across the 4kQ re- 
sistor resulting in a PTAT current of about 13liA. Because 
Q 10 matches Q 7 , and Q 3 matches Q 4 , equal PTAT currents 
flow in each of the four Q, - Q 4 legs. The current in the Q, 
leg biases a Vbe/12kQ current generator formed by Q u and 
Q 12 . The negative TC current from Q u sums at the output. 
The 4k£2 and 1 2kfi resistors are actively laser trimmed over 
temperature at wafer level to give an accurate zero TC 
output. NPN transistors Q 5 , Q s , and Q 9 cascode Q 7 and Q g for 
improved accuracy and output impedance. Likewise, J, and 
J 2 cascode Q 3 and Q 4 . Using FET cascodes rather than PNPs 
eliminates noise due to base current. The capacitor provides 
loop compensation. 

IOOliA was chosen as a practical value for the majority of 
applications. It is high enough to be used directly for sensor 
excitation in many instances, while it is low enough to be 
used in low power and battery powered applications where 
a higher current might be excessive. Also at higher output 
currents, thermal feedback on the chip and self heating 
would reduce the output impedance. 




FIGURE 3. The REF200 Current Source cell is powered 
from its input terminals. It achieves zero TC by 
summing a positive TC current from a bandgap 
cell with a negative TC current. 

Difet" Burr-Brown Corp. 



construct a current source of any value. The REF200 can be 
pin strapped for 50u.A, 200uA, 300|iA, or400|iA, in addition 
to lOOuA. 

For a 50(iA current sink, use the circuit shown in Figure 4. 
A 100|XA current source is tied to the mirror common. Since 
a current mirror output must equal its input, 50p:A flows in 
the input to ground, and the output is a 50|J.A current sink. 



negative ran wnn enner a resisxor ana current source, or a 
resistor biased zener. 




FIGURE 4. A 50(J.A Current Sink with compliance to ground 
can be made using one of the lOOixA current 
sources and the mirror from the REF200. 

PIN STRAPPING REF200 FOR: 
50uA Current Source 

For a 50(J.A current source, use the circuit shown in Figure 
5. In this circuit a current sink subtracts 50|iA from a second 
100|jA source leaving a 50(J.A source. Compliance is from 
below ground to within 2.5V of the positive rail. 




FIGURE 5. A 50uA Current Source with compliance from 
ground to +V S -2.5V can be made using both 
100|iA current sources and the mirror from the 
REF200. 




FIGURE 6. Compliance of the 50\xA Current Sink (Figure 5) 
can be extended to -V S +5V by referencing its 
bias point to the negative power supply rail using 
the other lOOuA current and a resistor. 




FIGURE 7. If you don't have a current source to spare, the 
50|jA Current Sink with compliance to -V S +5V 
can be biased using a zener diode. 

PIN STRAPPING REF200 FOR: 
200^A FLOATING CURRENT SOURCE 

A 200pA floating current source is formed by simply paral- 
leling the two current sources as shown in Figure 8. For 
compliance nearer to the negative rail, use the mirror as 
shown in Figure 9. The output of the mirror can swing about 
a volt closer to the negative rail than the current source 
alone. 




FIGURE 8. For a 200uA Floating Current Source simply 
parallel the two lOOuA current sources from the 
REF200. 




FIGURE 10. The two lOOuA Current Sources and Mirror in 
the REF200 can be connected to form a 300jiA 
floating current source. 




FIGURE 9. You can mirror the lOOuA or 200uA Current 
Sources from the REF200 for a lOOuA or 
200uA current sink with improved compli- 
ance. 

PIN STRAPPING REF200 FOR: 
300uA Floating Current Source 

A 300uA floating current source can be strapped together as 
shown in Figure 10. It is formed by paralleling a 200uA cur- 
rent source, made with one 100(iA source and the mirror, 
with the other lOOuA current source. The 200uA current 
source is made by connecting a lOOuA current source to the 
mirror input so lOOuA flows in the mirror output, and 200uA 
flows in the mirror common. 

PIN STRAPPING REF200 FOR: 
400uA Floating Current Source 

A 400uA floating current source can be strapped together as 
shown in Figure 11. It is basically the same as the 200uA 
current source of Figure 10, except that 200uA is fed into the 
mirror input. This 200^A is summed with the 200uA that 
flows in the mirror output for a total of 400uA. 




FIGURE 1 1. The two 100|aA Current Sources and Mirror in 
the REF200 can be connected to form a 400|iA 
floating current source. 

RESISTOR PROGRAMMABLE 

CURRENT SOURCES AND SINKS 

USING REF200 AND ONE EXTERNAL OP AMP: 

Current Source or Sink With Compliance 

to Power Supply Rail and Current Out >100|iA 

You can build a programmable current source of virtually 
any value using two resistors, an op amp, and a 100[iA 
current source as a reference. 

The current source shown in Figure 12 can be programmed 
to any value above the IOOjjA reference current. It has com- 
pliance all the way to the negative power supply rail. The 
lOOuA reference forces a voltage of lOOjiA • R, at the non- 
inverting input of the op amp. When using a Difet ® op amp 
as shown, input bias currents are negligible. The op amp 
forces the same voltage across R r If Rj is N • R 2 , the output 
current is (N+l) • 100|iA. So long as the op amps input 
common mode range and its output can swing to the nega- 
tive rail within the voltage drop across R , the current source 
can swing all the way to the negative rail. If the voltage drop 
across R, is large enough, any op amp can satisfy this 



requirement. Figure 13 shows the same circuit turned around 
to act as a current sink. It has compliance to the positive rail. 



0- 



OOuA 




l OUT =(N +1).100nA 



FIGURE 12. Current Source. 



0.01 nF : 




|U=(N +D- 100mA 



100mA 



-V s NOTE: (1 ) Burr-Brown" OPA602. 

FIGURE 13. Current Sink. 



FIGURES 12 and 13. For a programmable current source 
with any output current greater than 
100|iA and compliance to +V S or 
-V s , use a lOOuA current source as a 
reference along with an external op 
amp and two programming resistors. 



Current Source or Sink With Any Current Out 

For currents less than 100|iA, use the circuits shown in 
Figures 14 and 15. They can be programmed for virtually 
any current (either above or below lOOuA). In this case the 
IOOliA current source forms a reference across R, at the 
inverting input of the op amp. Since the reference is not con- 
nected to the output, its current does not add to the current 
output signal. So, if R, is N • R„ then output current is N • 
lOOuA. Because compliance of the 100|iA current source is 
2.5 V, the current source, Figure 14, can only comply within 
2.5V of the negative rail — even if the op amp can go further. 
Likewise the current sink, Figure 15, has a 2.5V compliance 
to the positive power supply rail. 



l^-N-IOOuA 




(1) 



< i \AAA~ — 



© 



0.01 mF 
100mA 



FIGURE 14. Current Source. 



© 



1^-N-IOOuA ■ 



100mA 




FIGURE 15. Current Sink. 

NOTE: (1) Burr-Brown* OPA602 or OPA128. 
EXAMPLES 



R, 


R 2 


'out 








100O 


10Mi2 


1nA 


iokn 


1M£2 


1MA 


iokn 


1k£2 


1mA 



UseOPA128 



FIGURES 14 and 15. If you don't need compliance to the 
power supply rail, this circuit using a 
100(0. A current source as a reference 
along with an external op amp and 
two programming resistors can pro- 
vide virtually any output current. 

Current Sources and Sinks 
Using Voltage References 

To make a current source with the best possible accuracy use 
a zener-based voltage reference. The REF200 uses a band- 
gap type reference to allow low voltage two-terminal opera- 
tion. Although this makes a more flexible general-purpose 
part with excellent performance, its ultimate temperature 
drift and stability cannot compare to the REF102 precision 
10.0V buried zener voltage reference. 



Make a current source from a voltage reference using the 
circuit shown in Figure 15A. The voltage follower connected 
op amp forces the voltage reference ground connection to be 
equal to the load voltage. The reference output then forces an 
accurate 10.0V across R, so that the current source output is 
10V/R,. 

Negative output compliance for the current source is limited 
by the op amp input common-mode range or output range 
(whichever is worse). When using the OPA111 on ±15V 
power supplies, the negative compliance is -10V. For com- 
pliance almost to the negative power supply rail, use a single- 
supply op amp such as the OPA1013. 

Positive output compliance is limited by the voltage refer- 
ence minimum +V S requirement. When using the REF102 on 
±15V power supplies, positive compliance is +3.5V. 

Make a current sink with a voltage reference using the circuit 
shown in Figure 15B. The op amp drives both the voltage 
reference ground connection and the current scaling resistor, 
R, , so that the voltage reference output is equal to the load 
voltage. This forces -10.0V across R, so that the current sink 
output is -10V/R r The R 2 , C, network provides local 
feedback around the op amp to assure loop stability. It also 
provides noise filtering. With the values shown, the reference 
noise is filtered by a single pole with f 3dB = 1/(2 X n X R 2 X 

C, )• 



Negative output compliance for the current sink is limited by 
the op amp and further reduced by the 10V drop across R,. 
When using the OPA1 1 1 on ±15V power supplies, negative 
compliance is only guaranteed to ground. When using the 
single-supply OPA1013 op amp, negative compliance is 
approximately -5V. 

Positive compliance is limited by the REF102, but is im- 
proved by the 10V across R . For a REF102 operating on 
±15V power supplies, the positive compliance is +10V 
(limited by the op amp common mode input range). 

Keep in mind that the ultimate accuracy of a voltage refer- 
ence based current source depends on the absolute accuracy 
of the current-scaling registor. The absolute TCR and stabil- 
ity of the resistor directly affect the current source tempera- 
ture drift and accuracy. This is in contrast to circuits using 
current source references, as shown in Figures 12 to 15, 
where accuracy depends only on the ratio accuracy of the 
resistors. It is much easier to get good resistor ratio accuracy 
than to get good absolute accuracy especially when using 
resistor networks. 

Although these current sources made with voltage references 
do not have the compliance range of the previous circuits, 
they may be the best choice where the utmost in accuracy is 
required. 



REF102 

+10V 
Out 

GND 




Load 



I 



Can be Connected to 
Ground or -V, 



FIGURE 15 A. Current Source using Voltage Reference and Op Amp. 




REF102 

+10V 
Out 

GND 



I 



i 1 Load i ^ 



1 



Can be Connected to 
Ground or +V_ 



FIGURE 15B. Current Sink using Voltage Reference and Op Amp. 



use the circuit shown in Figure 16. It is basically the same 
as the current source shown in Figure 12 except that R, is 
driven by a MOSFET. Since no current flows in the gate of 
the MOSFET or the inputs of the op amp, all current that 
enters the resistors (and no more) leaves. Therefore the 
current source is completely floating. 

The power supplies of the op amp in this circuit, as in the 
other circuits, must be connected to ±V $ . Also, the input and 
output common mode limitations of the op amp must be 
observed. 



■ High 

l OUT = (N + 1)-100uA 

f 



100nA 

T +V s 




1 1 Low 

NOTE: (1) Burr-Brown D/fef® OPA602. 

FIGURE 16. Use a IOOliA Current Source as a reference, an 
external op amp, two programming resistors, 
and a series pass element for a programmable 
floating curent source. 

Current Sources and Sinks and Current Mirrors 
Using an Amplifier and a Series Pass Element 

In some applications it may be desirable to make a current 
source or sink using a series pass element in addition to an 
op amp. This approach provides the benefits of cascoding 
and also allows arbitrarily high current outputs. 

The circuit used is the same as for the programmable 
floating current source shown in Figure 16. The difference 
is that the op amp power supply connection and reference 
input are both returned to a fixed potential. The result is 
either a current source or sink, but not a floating current 
source. The advantage is that the output can be any value, 
either more than, less than, or equal to the input reference. 
Also, a voltage source or even a variable voltage input can 
be used as a reference. The examples shown in Figures 17 
through 20 show IOOliA current sources used as references. 



highly accurate no matter what the mirror ratio. 

The pass element can bipolar, JFET, MOSFET, or a combi- 
nation. The examples recommend MOSFETS because their 
low gate current minimizes output error. Also, MOSFETs 
with very high current ratings are available, and require no 
additional drivers. 

In many cases bipolar devices are adequate and may be 
preferred due to their low cost and availability. With a 
bipolar device, the base current will add error to the output 
signal as discussed in the cascoding section. Using a darling- 
ton-connected bipolar device feeds the error current back 
into the signal path and reduces the error by the forward 
current gain (beta) of the input transistor. 

In some high temperature applications, darlington-connected 
bipolar transistors may have lower error than FETs. As a 
rule of thumb, the gate current of a FET or MOSFET 
doubles for every 8°C increase in temperature, whereas the 
beta of a bipolar device increases approximately 0.5%/°C. 
Therefore, when operating at 125°C, the gate current of a 
FET will be about 6000 times higher than at 25°C, while the 
base current of the bipolar will be 1 .5 times lower. 

When selecting the op amp for this application, pay particu- 
lar attention to input bias current, input common mode 
range, and output range. 

The bias current of the op amp adds to the input current, and 
subtracts from the output current. For a 1 : 1 mirror applica- 
tion, the error is only the mismatch of bias currents or I os of 
the amplifier. For other ratios, assume that the error is equal 
to the full amplifier bias current. For most applications, the 
error will be negligible if a low bias current Difet ® ampli- 
fier such as the Burr-Brown OPA602 is used. Its I B is lpA 
max. 

Be sure to observe the input common mode range limit of 
the op amp. For example, when using the OPA602 in a 
current sink application, the voltage between the op amp 
negative supply and its input must be at least 4V. In a split 
power supply application, R { and R 2 can be connected to 
ground, and the op amp negative supply can be connected to 
-5V or -15V and there is no problem. In a single supply 
application, or when R r R 2 , and the op amp's — V s are all 
connected to the negative power supply, a drop of at least 4V 
must be maintained across R,. 

Using a single supply op amp allows the input common 
mode range to go to 0V. Especially in single supply current 
mirror applications, it is often desirable for the input and 
output to go to zero. The OPA1013 has an input common- 
mode range which extends to its negative power supply, and 
its output will swing within a few mV of the negative supply. 
Although the OPA1013 has bipolar inputs, its bias current is 
low enough for most applications. 

Components R 3 , R 4 , and C ( form a compensation network to 
assure amplifier stability when driving the highly capacitive 
inputs of some MOSFETs. In many applications they can be 
omitted. 



CD 



100uA 




R, 

10kfl 



C, R, 
0.001 hF I 50QQ 

WW^ 



100mA 



N channel enhancement MOSFET 
r*=h Supertex, Siliconix, Motorola, etc. 
or 

2 X 2N2222 



R 2 

ion 



NOTE: Can be connected to -V s with 4V min across R,. 



FIGURE 17. Programmable Current Sink using series pass device. 



0-4mA In 




R, 
100Q 



0-40mA Out 



R, 

500Q 



C 

0.001 



aaa .^^ m cnannei ennan 

~Y VVV | p 3 ! Supertex, Siliconi: 

500fl 

vW 



-p. Ft 4 

1uF soon 

1 ^A; 



N channel enhancement MOSFET 
Siliconix, Motorola, etc. 
or 

2 X 2N2222 



To Ground or -V s a 



R, 

50Q 



FIGURE 1 8. Sinking Current Mirror using series pass device. 




© 



100nA 



ioon 



NOTE: Can be connected to 
+V. with 2V min across R,. 



Supertex, Siliconix, Motorola, etc. 
P channel enhancement MOSFET 
or 

2 x 2N3906 



|100mA 



FIGURE 19. Programmable Current Source using series pass device. 



11 



To Ground or +V S 




0-4mA In 




soon 
-AyW 



R 3 
loon 



-VW — l-cJ 



R 2 
son 



NOTE: The LF155 input common-mode range typically includes +V S , 
but this is not a guaranteed specification. 



Supertex, Siliconix, Motorola, etc. 
P channel enhancement MOSFET 
or 

2 x 2N3906 



-v. 




0-40mA Out 



FIGURE 20. Sourcing Current Mirror using series pass device. 

Floating Current Source With Current 

Out >100uA and No Separate Power Supply 

If a programmable current source is needed, and no separate 
power supply is available, consider the floating current 
source shown in Figure 21. Here the op amp power supplies 
are connected to the current source input terminals. The op 
amp quiescent current is part of the output current. 



© 



100uA 



High 
25mA 





100Q- 




100f!- 




R 3 ioon; 
ioon 



? R, 1 Okn 
(N • R 2 ) 




Low 



NOTE: Each amplifier 1/4 LM324. 



FIGURE 21. 25mA Floating Current Source using a quad 
single-supply op amp needs no external power 
supply. 

There are two special requirements. First, a single supply op 
amp must be used (an op amp with an input common mode 
range that includes the negative supply rail). Also the output 
current must be greater than the op amp quiescent current. 

The circuit is basically the same as Figure 12. The lOOuA 
current flowing through R, produces a floating voltage ref- 
erence at the non-inverting input of A,. The op amp quies- 



cent current flowing from its negative supply pin sums into 
the current flowing into R r The op amp outputs drive the 
additional current needed through R 2 so the voltage drop 
across it matches the voltage drop across R r If Rj is N • R 2 , 
the output current is (N+l) • lOOuA. With the values shown, 
the output current is 25mA. 

The op amp outputs are connected to R 2 through 100Q 
resistors. The current delivered by A produces an approxi- 
mate 0.5V voltage drop across R y The other three op amps 
are connected as voltage followers so that the same voltage 
is dropped across the other three 100Q resistors. The output 
current from each op amp is therefore equal and the load is 
shared equally. This technique allows any number of 10mA 
output op amps to be paralleled for high output current. 

CASCODING CURRENT SOURCES FOR 
IMPROVED OUTPUT IMPEDANCE, 
HIGH FREQUENCY PERFORMANCE, 
AND HIGH VOLTAGE COMPLIANCE 

Cascoding With FETs 

The output impedance and high frequency performance of 
any current source can be improved by cascoding. Starting 
with a precision current source like the REF200 or any of the 
variations previously discussed, it is relatively easy to build 
a current source to satisfy just about any need. 

Cascoding can also be used to increase high voltage compli- 
ance. High voltage compliance of a cascoded current source 
is limited solely by the voltage rating of the cascoding 
device. High voltage compliance of hundreds or even thou- 
sands of volts is possible. 

Cascoding is the buffering of the current source from the 
load by a series pass device as shown in Figure 22. Here an 
N channel JFET cascodes the current source from the output. 
The gate of the JFET is tied to ground, its source to the 
current source, and its drain to the load. Variations in the 
load voltage are taken up by the drain of the JFET while the 
source voltage remains relatively constant. In this way, the 
voltage drop across the current source remains constant 
regardless of voltage changes across the load. With no 
changes in the voltage across the current source, and with no 
current lost through the JFET drain approaches infinity. AC 
performance of the cascoded current sink approaches that of 
the JFET. 



Compliance to GND i 


1 'out 




|100uA 

i 




2N4340 


-a 


^) 100nA 


i 


'-v. 



FIGURE 22. Cascoded Current Sink with compliance to 
ground. 

Since the gate of the JFET is tied to ground, the output 
compliance is limited to near ground. If greater compliance 
is required for the current sink, the gate of the JFET can be 
referenced a few volts above the negative rail as shown in 
Figures 23 and 24. In Figure 23 the gate reference is derived 
from a resistor biased from the second current source. If a 
current source is not available, use a resistor biased zener as 
shown in Figure 24. 



Compliance to -V s +5V 



CD 



0.01 u.F =p 



100uA 



1 



51k£2 



CD 



100U.A 



2N4340 



100uA 



FIGURE 23. Cascoded Current Sink with compliance to 
-V S +5V (using zener diode for bias). 



Compliance to -V s +5V 



27k£2 



OUT 

100U.A 



1N4689 7? 5.1V 



CD 



2N4340 



100U.A 



FIGURE 24. Cascoded Current Sink with compliance to 
-V S +5V (using zener diode for bias). 

To implement current sources, turn the circuits around and 
use P channel JFETs as shown in Figures 25 through 27. 



Compliance to GND 



CD 



100nA 



| oj~ 2N511 



100nA 



FIGURE 25. Cascoded Current Source with compliance to 
ground. 



Compliance to +V S -5V 



0.01 nF 



51 kn 



100nA 
1/2 REF200 



CD 



■of 2N5116 
100U.A 



FIGURE 26. Cascoded Current Source with compliance to 
-V S +5V (using current source and resistor for 
bias). 



Compliance to +V S -5V 



1N4689 



*5. 



IV 



CD 



100^A 



27k£2 



2N5116 
100nA 



FIGURE 27. Cascoded Current Source with compliance to 
-V S +5V (using zener diode for bias). 

In most applications, JFETs make the best cascoding devices, 
but bipolar transistors and MOSFETs can also be used. 
MOSFETs can provide equivalent AC and DC performance 
to JFETs. Bipolar devices may offer better high frequency 
performance, but have a limited DC output impedance. The 
output impedance of a bipolar cascoded current source is lim- 
ited by changes in base current with changes in collector 
voltage. The maximum output impedance of a bipolar cas- 
coded current source is b • R , where b is the current gain of 
the bipolar device, and R Q is its output impedance 



the REF200 and a few external devices, sources of 200|iA, 
300liA, and 400uA can be strapped together. 

The 200liA floating cascoded current source is shown in 
Figure 28. It is made using a cascoded current source and a 
cascoded current sink each biasing the other. Low voltage 
compliance is limited to about 8V by the sum of the gate 
reference voltages. High voltage compliance is limited by 
the lower voltage rated FET. 



100uA Q^) 



High 



40kn 



2N5116 



0.01 uF dp 



d= 0.01 uF 



2N4340 



•40kO 



^) 100uA 



■ Low 

Regulation (15V-30V) = 0.00005%A/ (10G£2) 



FIGURE 28. Cascoded 200|iA Floating Current Source. 

300 li A Floating Cascoded 
Current Source Using REF200 

The 300|iA floating current source is shown in Figure 29. It 
is similar to the 200(iA current source shown in Figure 28, 
except the current source in the cascoded sink section is 
derived from the mirror. The gate reference for the sink cas- 
code is derived from the series combination of the mirror 
input and a 27kQ resistor. The extra IOOjxA is obtained by 
summing the other IOOliA current source into the sink 
cascode device. Compliance limits are the same as for the 
200uA cascoded source. 

400u.A Floating Cascoded 
Current Source Using REF200 

The 400liA floating cascoded current source is shown in 
Figure 30. It is the similar to the 300(iA cascoded current 
source, except that the mirror is driven by a cascoded 200|O.A 
current source derived by the parallel combination of the 
two current sources in the REF200. The low voltage compli- 
ance of this circuit is about IV better than the previous two 
circuits because the mirror compliance is about IV better. 
High voltage compliance is still limited only by the break- 
down of the lower rated FET. 



100uA 



20kn; 



2N5116 



0.01 jiF 



0.01 uF 



2N4340 



: 27k£2 



4 

Out 



REF200 
Mirror 



© 



Com 
3 



100uA 



■ Low 

Regulation (15V-30V) = 0.00003%/V (10GO) 



FIGURE 29. Cascoded 300|iA Floating Current Source. 



100uA Q ^)l00uA Q ^) 



2N5116 



High 



20kn : 



d= 0.01 uF 



2N4340 
4 

Out 



REF200 
Mirror 



Com 
3 



■ Low 

Regulation (15V-30V) = 0.00025%/V (10GO) 



FIGURE 30. Cascoded 400U.A Floating Current Source. 

NOISE REDUCTION OF CURRENT SOURCES 

In many modem systems, noise is the ultimate limit 
to accuracy. And in some systems, performance can be im- 
proved with a lower noise current source. Current source 
noise can be reduced by filtering, using the same basic prin- 
cipals used for noise reduction of voltage references. Reduc- 
ing the noise bandwidth by filtering can reduce the total 
noise by the square root of the bandwidth reduction. 



One current source noise reduction circuit is shown in 
Figure 31. It is basically a FET cascode circuit with the 
addition of an RC noise filtering circuit. The FET, as biased 
by the 100|iA current source, forces an accurate DC voltage 
across the circuit. 

Without the capacitor, noise from the current source would 
feed directly through to the output. The capacitor filters the 
noise at a -3dB frequency of 1/(2 • k • R« C), or about 30Hz 
in this example. Filtering below this frequency will not 
reduce noise further, since the 30Hz pole is already below 
the 1/f corner of the current source, and noise can not be 
reduced by filtering in the 1/f region. Also, the noise of the 
FET and resistor are not filtered. Still, using this circuit, the 
noise is reduced from the typical 20pA/VHz to less than 
lpA/VHl 



In addition io noise reduction, these circuits have the other 
advantages of a FET cascoded current sink; output imped- 
ance in the GQ region, improved AC performance, and high 
voltage compliance limited only by the FET. 




FIGURE 31. Current noise from a current source can be 
filtered using this circuit. 

The value of the resistor used in the noise reduction circuit 
determines its ultimate performance. Although the noise of 
the resistor increases with the square root of its value, its 
noise degenerating effect reduces noise linearly. Therefore, 
the noise is reduced by the square root of the resistor 
increase. The practical limit for the noise reduction is the 
voltage drop which can be placed across the resistor. 

Mathematically, current noise due to the resistor is the 
resistor thermal noise divided by the resistor value. 



(i - 3 - io ;' 0) ^ = (i.3.io-' )/ vr- 



R 



With a 50 kQ resistor, the minimum theoretical noise is 
.6pA/VHz, with lOkQ, it is 1.3pA/VPIz. Noise measurements 
of the circuit using both lOkQ and 50k£2 resistors and the 
Siliconix J109 FET agree with these theoretical numbers 
within 20%. 

The noise reduction circuit in Figure 31 has a low voltage 
compliance limit near ground. For compliance below ground, 
use the circuit shown in Figure 32. 




FIGURE 32. Current Noise Filtering Circuit with compli- 
ance below ground. 



APPLICATIONS OF FIXED 
CURRENT SOURCES 

VOLTAGE REFERENCES 
USING CURRENT SOURCES 

Many design problems can be easily solved with inexpen- 
sive, easy-to-use current sources like the REF200. Although 
applications are endless, the collection of circuits that fol- 
lows is intended to stimulate your thinking in several broad 
categories: fixed voltage references, floating voltage refer- 
ences, current excitation, fixed current references, steered 
current references, and biasing. 

Current sources are a versatile means of forming voltage 
references. Why not just use a voltage reference? With a 
current source, a single resistor provides a programmable 
voltage source of any value. Low voltage references are 
often needed, and with this approach, it's as easy to get a 
lmV reference as it is to get a 10V reference. Also, the 
voltage can be referenced anywhere — to the positive rail, the 
negative rail, or floating anywhere in between. 

When impedances driven by the voltage reference are high, 
the voltage output from the resistor derived voltage refer- 
ence can be used directly. The 100u.V reference shown in 
Figure 33 can be used directly in voltage-to-frequency con- 
verter (VFC) auto-zero applications where an off-zero refer- 
ence is needed (since zero frequency would take forever to 
measure, off-zero techniques are often used for calibrating 
VFCs). Where a lower output impedance is needed, a simple 
buffer can be added as shown in Figure 34. 



15 




FIGURE 33. IOOjiV Reference for VFC off-zeroing. 




FIGURE 34. Buffered Voltage Reference. 

For a floating voltage reference, simply drive the reference 
low side (grounded side of the voltage-setting resistor) as 
shown in Figure 34A. Notice that in addition to the swing 
limitations imposed by the op amp input common-mode 
range and output range, the reference high side swing is 
limited to 2.5V from the positive rail by the REF200's 
minimum compliance voltage. The low side swing is limited 
only by the op amp. If the reference voltage is more than 
about 3V this limitation can be eliminated by adding gain as 
shown in Figure 34B. In this example, the IV across the 
reference setting-registor is amplified to 5V at the output. 
Since there is always 4V between the output and the op amp 
inputs, the high-side swing is not limited by the current 
source compliance or the op amp input common mode 
range. It is limited only by the op amp out put swing 
capability. 

Where the voltage reference is lower than about 3V, the high 
side compliance will still be limited by the current source 
compliance. In these situations, consider the circuit shown in 
Figure 34C. In this case, the op amp noninverting input is 
driven while the current source connects to the other op amp 
input and a voltage setting resistor with its other terminal 



connected to the output. High-side compliance is limited 
only by the op amp. Another advantage of this circuit is its 
high input inpedance. The disavantage is limited low side 
compliance. Current source compliance limits swing to the 
negative rail to 2.5V — regardless of the op amp input 
common mode range. 



100nA 







10k£2 ^ d= 0.01 (iF 




FIGURE 34A. Floating Voltage Reference. 



100nA 



+V 5 



© 



10.2k£2 




0.01 ■ 

10k£2 < X=nF< 2.55k£J 



FIGURE 34B. Floating Voltage Reference with high-side 
compliance limited only by op amp output 
swing capability. 



100nA 




FIGURE 34C. Floating Low Voltage Reference with high 
impedance input drive and high-side output 
compliance limited only by op amp output 
swing capability. 



OP AMP OFFSET 

ADJUSTMENT USING 5mV REFERENCE 

Op amp offset adjustment circuits are another application for 
millivolt level references. Many op amps, especially duals 
and quads, have no built-in provision for offset adjustment. 
Even when offset adjustment pins are provided, using them 
can degrade offset voltage drift and stability (e.g. the drift of 
a typical bipolar input op amp is increased 3(J.V/°C for each 
millivolt of offset adjustment). External offset adjustment 
circuits are commonly used to solve these problems. 

Conventional external offset adjustment circuits can add 
problems of their own. Many of these circuits use the op amp 
power supplies as references. Power supply variation feeds 
directly into the op amp input. This error appears as poor 
power supply rejection. Likewise, noise from the power 
supplies appears as op amp input referred noise. 



The circuits shown in Figures 35 and 36 solve these prob- 
lems. REF200 current sources provide regulated ±5mV ref- 
erences for stable offset adjustment. This approach provides 
a truly precision offset adjustment free from problems asso- 
ciated with power supply variations, noise, and drift. 

The circuit shown in Figure 35 uses a pair of 51 £2 resistors 
connected to ground to establish the ±5mV reference. A pot 
connected across this reference allows a +5mV offset adjust- 
ment range. Additional pots can be connected, but be sure to 
maintain a parallel resistance >50Q to get >±5mV range. 

The second circuit, Figure 36, uses a special potentiometer 
manufactured by Boums. It is especially designed for op 
amp offset adjustment. It has a tap at the center of the 
element which can be connected to ground. Using this con- 
nection eliminates the 51Q resistors needed in the first 
circuit. 



! +Vs 

(j^) 100nA 



R 8 

■VW — i 



5m • 



< > ° ther 

"T* Amps 




Op Amp to be Adjusted 



51£2 ■ 



2kn Linear 



100uA 

-v. 



Offset Adjustment Range = ±5mV 



FIGURE 35. Op Amp Offset Adjustment Circuit uses the two lOOuA current sources from a REF200 to provide accurate +5mV 
references. 



100nA 

V. 




^oon 

Bourns Trimpot* 




Op Amp to be Adjusted 



Q ^) 100uA 



Vout = v, n -(-R b /R a ) 

Offset Adjustment Range = ±5mV 



FIGURE 36. Op amp offset adjustment circuit using Boums Trimpot®. 



a iiuuuug ivi^i^nv.^ uppn^miun. raetc, a pan Ui CU11C11L 

sources is used to provide a floating bipolar window voltage 
driven by the V CENTER input. V Q is low when V { is either 
above V CENTER + lOOuA • R, or below V CENTER - 100|aA • R. 
Otherwise, V Q is high. By using different values for the 
programming resistors, the threshold can be set asymmetri- 



is no error due to wire 



cally around V 



if desired. 



RTD EXCITATION USING CURRENT REFERENCE 

Current sources are often used for excitation of resistor type 
sensors such as RTDs. If the RTD is located remotely, as it 
often is, voltage drops in the interconnecting wire can cause 



in the sense 
resistance. 

One problem is that the additional wiring can be very 
expensive. The three wire circuit shown in Figure 38 saves 
one wire. 200|iA is used for excitation of a lk£2 RTD, and 
a matching current from the current mirror is forced in the 
ground connection. The voltage drops through the two wires 
cancel thereby eliminating error. 

Notice also, that one common wire (shown as a shield) can 
serve multiple sensors. Each additional RTD only needs one 
additional pair of wires. 



CD 



Center" 



0.01 nF=: < R 



o.oinF : 



100nA 



-v. 



f +5V 



ikn 




1/2 LM393 




1/2 LM393 



100nA 



The Window 

h=3 o 



CENTER 

„_L.__L 
-V. +v w 
v, N 

V w = 100(iA • R 



FIGURE 37. Window comparator with voltage programmable window center, and resistor programmable window width. 



Cable Shield 



RTD ' 



a 



2 



INA110 

Instrumentation Amplifier 



200uA 
Reference 
Current 



B 




| 200uA 
| Compensation 
Current 



REF200 



-v. 



V w = Gain • 200uA • A RTD 



FIGURE 38. RTD excitation with three-wire lead resistance compensation. 



DEAD BAND CIRCUITS 
USING CURRENT REFERENCE 

Servo control systems frequently use dead-band and limiting 
circuits. The precision dead-band circuit shown in Figures 
39 and 40 demonstrates the use of a current source as a fixed 
reference. To understand how it works, notice that, without 
the current reference, the circuit is an inverting half wave 
rectifier. Positive inputs drive the op amp output negative 
and feedback is through forward biased D . No current flows 
through reverse biased D,, and the output is held at virtual 
ground by R,. 

Negative inputs forward bias D, and drive the output posi- 
tive. Feedback to the output through R, eliminates error due 
to the diode drop, and the circuit functions as a precision 



unity gain inverter (V Q = -V,). (Adding the current reference 
pre-biases to the input so that the output remains at virtual 
ground until the input current through R l exceeds 100|iA.) 
The output is zero (dead) until V, < +100(iA • R r An 
alternate approach would be to pre-bias the input through a 
precision resistor connected to a voltage reference, but that 
would add noise gain increasing offset, drift, and noise at the 
output. 

For a negative dead-band use the circuit shown in Figure 40. 
It's the same circuit with the diodes reversed. 

For a double dead-band, use the circuit shown in Figure 41. 
It uses both the positive and negative dead-band circuits 
summed together by a third amplifier. 



50k£J 



CD 



+15V 



100nA 



D, 1N4148 

-M> — 



R 2 

50kn 




D 2 
1N4148 




-r +10 



— +5 



+5 +10 



V, >• 
V,<- 



■5V : V c 
■5V : V„ 



-V, -5V 



— -10 



(Dead to 100uA • R,) 



FIGURE 39. Precision positive dead-band circuit. 



V IN 



3, 

50kn 



R 2 

50kO 



100nA 



-15V 







1N4148 

— K} 



; — 



10pF 




1N4148 

HO — 



-10 



V, < 5V : V D = 

V, > 5V : V = 5V - V, 

(Dead to-100nA • R,) 



"OUT 

-r +10 

; 

-r +5 



~j 5 

-f- -10 




19 



FIGURE 40. Precision negative dead-band circuit. 



+15V 
f 



R 
50kft 



)100jiA 



1N4148 



R 

50kn 



10pF 
OPA602 




1N4148 

— W- 



R 
50kf! 

-vW- 



100nA 



-15V 







1N4148 



R 

50kQ 

VvV- 



10pF 
OPA60§ 




1N4148 

-w — ■ 



+10 



-r +5 



-10 

•I- 




+5 +10 



4- -5 



-|- -10 



iokn 

iokn 
-vW- 



iokn 




OPA60: 



V, > 5V: V - V, - 5V 
V, < -5V: V D = V, + 5V 
(Dead to±100nA • R,) 



FIGURE 41. Precision double dead-band circuit. 



BIDIRECTIONAL CURRENT SOURCES 

One of the advantages in working with currents is that they 
can be steered by diodes or switches without error. As long 
as no current is lost through leakage, voltage drops in series 
with current signals do not diminish their accuracy. 

The bidirectional current source shown in Figure 42 is a 
versatile circuit building block and an excellent example of 
diode steering. This two-terminal element is basically a full- 
wave bridge rectifier circuit with a current source connected 
between its DC terminals. A positive signal on the left 
terminal with respect to the right reverse biases D 3 and D 4 
and accurately steers current through D ] and D r A negative 
signal reverses the situation and accurately steers the same 
current in the opposite direction. 

For one diode drop better compliance, use the bidirectional 
current source shown in Figure 43. The disadvantages of this 
circuit are that two current sources are required, and the 
inherent current matching of the previous circuit is lost. 



D, 



D 3 

■Kh 



100uA 



Bidirectional 
Current Source 



NOTE: All diodes = 1N4148. 



FIGURE 42. Bidirectional current source. 



100uA 



Bidirectional 
Current Source 



100uA 



NOTE: All diodes = 1N4148. 



FIGURE 43. Bidirectional current source with improved 
compliance. 

LIMITING CIRCUITS USING 
BIDIRECTIONAL CURRENT SOURCES 

The precision double limiting circuit shown in Figure 44 
puts the bidirectional current source to work. To understand 
how this circuit works, notice that without R it functions as 
a precision unity-gain amplifier. The input signal is con- 
nected to the non-inverting terminal of A . Feedback to the 
inverting terminal is through the bidirectional current source, 
voltage-follower connected A 2 , and the IkQ. resistor. When 
less than lOOuA is demanded from the current source, it 
saturates and the total voltage drop across the bidirectional 
current source is less than about 2V plus two diode drops. 
Since no current flows in the IkQ. resistor, the circuit output 
voltage must equal the input voltage and errors due to A, and 
the drop across the current source are eliminated. The lk- 
lOOpF network provides compensation for the extra phase 
shift in the feedback loop. 



When R, is added, the circuit still functions as a follower for 
small signals where the current through R i is less than 
100(1 A. When the current reaches 100|iA, the current source 
becomes active and limits the output voltage. With the 
bidirectional current source, the circuit limits symmetrically 
in both directions. 



100pF dp 




Vcot'V,,, (-5V<V 1N <5V) 



100uA 
See Figures 
42,43 




:5V(V, N >5V) 
:-5V (V, N <-5V) 
, o = 100uA-R) 



-10 

-2.5V (R = 25kn)__ 
-5.0V (R = 50kfi) 
-7.5V (R = 75kfl) ,- 




7.5V (R = 75k£i) 



5.0V (R - 50k£i) 



2.5V (R = 25k£l) 



FIGURE 44. Precision double limiting circuit. 



100pF d= 




1kQ 



1N4148 

-fO— 




V ut = V in (V, N <5V) 
V OUT = 5V (V lN >5V) 
(V^-IOOnA-R) 



■e- 

100uA 




R 

: 50W2 



7.5V (R = 75W2) 
5.0V (R = 50kfi) 



2.5V (R = 25kH) 



FIGURE 45. Precision limiting circuit. 



direction, reverse the polarity of the current source and 
diode. 

PRECISION TRIANGLE WAVEFORM GENERATOR 
USING BIDIRECTIONAL CURRENT SOURCES 

The precision triangle waveform generator shown in Figure 
46 makes use of two bidirectional current sources. One 
steers a precision current signal into the integrating capacitor 
connected to the inverting input of the op amp. The other 
steers a precision current into the lOkQ resistor connected to 
the positive op amp terminal to provide ±1 V hysteresis. The 
result is a relaxation oscillator with precision triangle and 
square wave outputs of ±1V. 





me pictision uuiy cycie mouuiaior suown in ngure f / is a 
variation of the triangle generator. Here the integrating 
capacitor is replaced by a true integrator formed by A, and 
C. This allows the summation of a ground referenced signal 
through the 100k£2 input resistor. With no input signal, the 
output is a square wave with 50% duty cycle. Input signals 
sum into the integrator through the lOOkQ resistor. The 
integrator then slews faster in one direction, and slower in 
the other. The result is a linear duty cycle modulation of the 
output signal. The modulator is said to be duty cycle rather 
than pulse width because the output frequency varies some- 
what with input signal. For a constant frequency duty cycle 
modulator add a resistor in series with the inverting input of 
A 2 and drive that input with a resistor coupled clock signal. 



100uA Bidirectional 
See Figures 42,43 




100|iA Bidirectional 
See Figures 42,43 



Triangle Output 




Square Output 



2Vp-p 



Ft 

10kfl 



Frequency = 1/4RC (Hz) 

Frequency = 25/C (Hz) - Where: C is in uF and R = 10W2 



FIGURE 46. Precision triangle waveform generator. 




V 1N = 10V: Duty Cycle = 100% 
V 1N = OV: Duty Cycle = 50% 
V 1N = -10V: Duty Cycle = 0% 



1 0OuA Bidirectional 
See Figures 42,43 



12Vp-p 
Duty Cycle Out 



:60kn 



lation i 



FIGURE 47. Precision duty-cycle modulation circuit. 



Notice that the duty-cycle modulator has a true integrating 
input. This is in contrast to conventional modulators which 
simply use a comparator connected between the input signal 
and a precision triangle wave. With the conventional ap- 
proach, at crossing, input noise feeds through at the com- 
parator bandwidth resulting in jitter. Not only does the 
integrating input filter out input noise, it can be synchro- 
nized to input noise (such as 60Hz), completely notching out 
its effect. If integration takes place over one or more com- 
plete cycles of the noise signal, the undulations of the noise 
signal are exactly averaged out. 

SLEW RATE LIMITER 

In some applications, especially when driving inductors, it is 
necessary to limit the signal slew rate. The rate limiting 
circuit shown in Figure 48 uses a diode bridge for current 
steering in a different way. Here two current sources are 
connected, one to the positive terminal and one to the 
negative terminal, of the bridge. Without the capacitor, the 
circuit would act as a unity gain inverting amplifier. Feed- 
back through the 10k£2- lOkQ resistor network drives the 
left side of the bridge. The right side of the bridge follows, 
driving the op amp inverting input. Voltage offset due to 
diode mismatch can be mitigated by using a monolithic 
bridge such as the one specified. When the integrator capaci- 
tor is added, charging and discharging current must flow to 
maintain the virtual ground. But when that current exceeds 
lOOuA, the bridge reverse biases limiting the output slew 
rate to lOOuA/C regardless of input signal rate. 

SINGLE SUPPLY INSTRUMENTATION AMPLIFIER 

Single power supply systems are common and the need for 
instrumentation amplifiers (IAs) to operate in this environ- 



ment is critical. While single supply op amps have been 
available for many years, single supply IAs have not. What's 
more, single supply IAs can not be made by simply using 
single supply op amps in the traditional manner. In a con- 
ventional IA topology the outputs as well as the inputs 
would need to swing to the negative rail. Although some op 
amps come close, no amplifier output can swing all the way 
to its power supply rail, especially when driving a load. 

The single supply IA circuit shown in Figure 49 solves this 
problem by simply level shifting the input signal up by a 
Vbe with a matched pair of matched PNP input transistors. 
The transistors are biased as emitter followers by the lOOuA. 
current sources in a REF200. The ensuing circuit is a tradi- 
tional three op amp LA. OPA1013s are used for input ampli- 
fiers because they are designed for single supply operation 
and their output can also swing near the negative rail. The 
Burr-Brown LNA105 is used as a difference amplifier. All 
critical resistor matching is taken care of by the INA105. 
The common mode range of the single supply IA typically 
extends to 0.5V below the negative rail with a typical CMR 
better than 86dB. 

VOLTAGE CONTROLLED 
CURRENT SOURCE USING INA105 

The modified Howland current pump (Figures 50-52) is an 
extremely versatile voltage controlled current source. Since 
it has differential inputs, you can ground one input and drive 
the other to get either an inverting or noninverting transfer 
function. If you drive both inputs, the output current will be 
proportional to the voltage difference between the inputs. 

What's more, unlike current sources made with a series pass 
element, which can either sink or source current, this current 
source has a bipolar output. It can both sink and source 
current. 



10kO 







100uA 



10W2 



xz 

V 



V 




V = -V 

V V IN 

Rate Limit = 100uA/C 



Diodes: 1 N4148, or Burr-Brown PW5740-3 for better V„ 



© 



lOOfiA 



FIGURE 48. Rate limiting circuit. 



23 



+ln i 



100uA 




1/2OPA1013 




(J ^) 100uA 



1/2OPA1013 



+V S 

M5V) 



PMI 
MAT03^|~ 



i -In 



' -v. 

(-15V) 



V o = + m - (-In) 

Input Common Mode Range: to -V s (and below). 



Burr-Brown INA105 




° 



FIGURE 49. Single-supply instrumentation amplifier. 



Use of this circuit was limited in the past due to the critical 
resistor matching and resistor TCR tracking requirements. 
By using the INA105 difference amplifier, the circuit can be 
easily implemented with the addition of two 1% resistors. 
Matching of the external resistors is important, but since 
they add to the internal 25k£2 resistors, the matching require- 
ment is divided down by the ratio of resistance. 

Output impedance of the current source is proportional to 
the common mode rejection (CMR) of the difference ampli- 
fier. Mismatch of feedback resistors in the difference ampli- 



INA105 



VW- 



25kn 




25kO 



25kQ 



U.^V, - V 2 ) (1/25k+ 1/R) 



FIGURE 50. Voltage-controlled current source with differ- 
ential inputs and bipolar output. 



fier caused by the external resistors will degrade CMR and 
lower the current source output impedance. Resistor match 
of 0.002% is required for lOOdB CMR in a unity gain differ- 
ence amplifier. Depending on the value of the external 
resistor and output impedance requirement, it may be neces- 
sary to trim the external resistor. 

When the value of the external resister becomes large 
consider the alternate circuit shown in Figure. 51. 



INA105 

vw— t — m- 



25kn 



25kfl 



25kQ 

vw- 




25kiJ 

-vW- 




U =(V,-V 2 )/R 



FIGURE 5 1 . Voltage-controlled current source with differ- 
ential inputs and bipolar output and circuit to 
eliminate feedback resistor error. 



You need an extra amplifier to drive the feedback resistor in 
the difference amplifier, but only one external resistor is 
required, and no matching or trimming is needed. 

In any case the output impedance of the current source can 
be approximated by the following relationship: 



Z Q = R x • 10 [CMRR/201 



Where: 



Z Q = equivalent output impedance of current source [Q] 
CMRR = difference amp common mode rejection ratio [dB] 

(for Figure 50) 
R x = parallel combination of external resistor and 25k£l 

R • 25kQ 

R x = 

R + 25kQ 

(for Figure 51) 
R x = external resistor [Q] 

The INA105 can source 20mA and sink 5mA. If higher 
output current is required, add a current buffer as shown in 
Figure 52. The OPA633 shown allows output currents up to 
±100mA. Since the buffer is within the feedback loop, its 
DC errors have no effect on the accuracy of the current 
source. When using other buffers make sure that their 
bandwidth is large enough not to degrade circuit stability. 

If you want voltage gain in the voltage to current converter, 
use the INA106 for a gain-of-ten difference amplifier. 

Don't forget that source impedance adds directly to the input 
resistors of the difference amplifier which can degrade its 
performance. A source impedance mismatch of 5Q. will 
degrade the CMRR of the INA105 to 80dB. If you are 
driving the circuit from an amplifier or other low impedance 
source, this should not be a problem. If you have higher 
source impedances, buffer the driven input(s) of the differ- 
ence amplifier, or use an instrumentation amplifier such as 
the INA110 instead of a difference amplifier. 



25kn 



INA105 



25kQ 



-vVV^ 

25kft 



25kQ 




Ut = (V,-V 2 ) (1/25K+1/R) 



FIGURE 52. Voltage-controlled current source with differ- 
ential inputs and current boosted bipolar out- 
put. 



VOLTAGE CONTROLLED CURRENT 
SOURCE WITH INSTRUMENTATION 
AMPLIFIER INPUT— THE XTR101 

The XTR101 is a floating current source designed for two 
wire 4-20mA current loop applications. It is a voltage con- 
trolled current source with a precision instrumentation 
amplifier input. It also contains two matched 1mA current 
sources which makes it suited for remote signal conditioning 
of a variety of transducers such as thermocouples, RTDs 
thermistors, and strain gauge bridges. 

Figure 53 shows the XTR101 connected as a temperature 
controlled current source. The temperature sensing element 
is a thermocouple, and cold junction compensation is pro- 
vided by the diode. 

The product data sheet for the XTR101, (PDS-627) gives 
operating details for the device and shows several other 
applications. 

SINGLE SUPPLY VOLTAGE 

CONTROLLED CURRENT SOURCE— THE XTR110 

The XTR1 10 is a precision single supply voltage to current 
converter. Although it is designed specifically for three wire 
4-20mA current transmission it can also be used in more 
general voltage to current source applications. As shown in 
Figure 54, it contains: a precision 10.0V reference and input 
resistor network for span offsetting (0V In = 4mA Out), a 
voltage to current converter for converting a ground refer- 
enced input signal to an output current sink, and a current 
mirror for turning the output of the current sink into a current 
source. 

The current mirror has a gain ratio of 10:1 and uses an 
external pass transistor to minimize internal thermal feed- 
back and improve accuracy. Since the mirror transistor is 
external, an external mirror ratio setting resistor can be 
added for an arbitrarily high output current. 

Both the voltage to current converter, and the current mirror 
use single supply op amps so that the input and output 
signals can go to zero. In the case of the mirror op amp, the 
common mode range goes to the positive power supply rail 
rather than common. 

The following table shows a range of input-output spans that 
is available simply by pin strapping the XTR1 10. 



Input 


Output 












Range 


Range 


Pin 


Pin 


Pin 


Pin 


Pin 


(V) 


(mA) 


3 


4 


5 


9 


10 


0-10 


0-20 


Com 


Input 


Com 


Com 


Com 


2-10 


4-20 


Com 


Input 


Com 


Com 


Com 


0-10 


4-20 


+10 


Input 


Com 


Com 


Open 


0-10 


5-25 


+10 


Input 


Com 


Com 


Com 


0-5 


0-20 


Com 


Com 


Input 


Com 


Com 


1-5 


4-20 


Com 


Com 


Input 


Com 


Com 


0-5 


4-20 


+10 


Com 


Input 


Com 


Open 


0-5 


5-25 


+10 


Com 


Input 


Com 


Com 



For more details and applications, request product data sheet PDS-555. 



NOTE: (1) R s = 152f2 to give 4-20mA 
Out for 58mV in Type J thermocouple 
with 1 000°C temperature change. 




FIGURE 53. Temperature-controlled current source using XTR101. 




FIGURE 54. Precision single-supply voltage-to-current source transmitter— the XTR110. 



CURRENT RECEIVER WITH 
COMPLIANCE TO BOTH POWER 
SUPPLY RAILS USING THE INA105 

Measuring current signals can be as simple as feeding the 
current into a precision resistor (V = I • R). If needed, the 
voltage developed across the resistor can be buffered or am- 
plified with an operational amplifier. 

If common-mode signals are present on the current return 
end of the sense resistor, an instrumentation amplifier (IA) 
can be used to reject the common mode signal and reference 
the output signal to ground. However, a limitation of con- 
ventional IAs is that their common mode input range is 
limited to less than 10V. 

When you need to reference the current return of the sense 
resistor to a higher common mode voltage, consider one of 
the following difference amplifiers. 





Input Common 


Other 


Model 


Mode Range 


Features 




(1) 




INA105 


± 20V 




INA117 


±200V 




RCV420 


± 40V 


(2) 



NOTES: (1) Common-mode input range specified for operation on 
standard ±15V power supplies. (2) Also contains a precision 
reference and offsetting circuitry to get 0-5V outputs with 4-20mA 
inputs. 

Figure 55 shows a current receiver using the INA105. The 
input current signal is sensed across 100Q resistor, R s , 
connected to the negative power supply rail. Connecting the 
sense resistor to a power supply rail instead of ground 
maximizes the voltage drop available across the current 
transmitter. 

Voltage divider action of the feedback resistors within the 
INA105 divide the common-mode input by two. Therefore, 
common mode input signals of up to ±20V are attenuated to 
an acceptable level of no more than ±10V at the op amp 
inputs. 



to 1 0mA 



ioon : 



100Q 



INA105 



V\/\A- 
25kQ 




25kO 



25kn 



^OUT 

0tO-1V 



Matching resistor, R M , preserves the resistance match of the 
INA105 and maintains its high common-mode rejection 
(CMR). Because 10fX2 is small compared to the 25kQ 
difference resistors, a 1 % tolerance is sufficient to maintain 
86dB CMR. 

The INA105 references the output signal to ground with a 
gain of one. For a 0-1 0mA input the output is to —IV (a 
transfer function of -100V/A). If a positive transfer function 
is desired, interchange the input pins of the difference 
amplifier. To reference current signals to the positive rail, 
simply connect the sense resistor and the other difference 
amplifier input to that point. 

The 25k£2 input impedance of the difference amplifier 
causes a slight error by shunting a portion of the input 
current signal. In the noninverting configuration, the match- 
ing resistor lowers the difference amplifier gain, but since 
the shunting input impedance of the noninverting input is 
50kQ, for a unity gain difference amp, the error turns out to 
be the same. For a 100Q sense resistor, the error is a 
approximately 0.4%. For better accuracy, select a slightly 
higher value sense resistor to compensate for the error 
according to the following equation. 

25k • X 



s 25k - X 



Where: 

X = desired transfer function [V/A] 
For example: 

For lV/lOmA (100V/A) from Figure 55: 
R s = R M = 100.4Q 

POWER AMP LOAD CURRENT 

MONITORING USING THE INA105 OR THE INA117 

The INA1 17 is a difference amplifier similar to the INA105 
except that it has a 20/1 input divider allowing a ±200 V 
common mode input range. It also has an internal gain of 20 
providing an overall gain of one. The penalty is that ampli- 
fier DC errors, and resistor and amplifier noise are amplified 
by 20. Still for 200V applications that do not require gal- 
vanic isolation its has better performance than isolation 
amplifiers, and it does not require an isolated power supply. 

Figure 56 shows a circuit for measuring load current in a 
bridge amplifier application using the INA117. At low fre- 
quencies, a sense resistor could be inserted in series with the 
load, and an instrumentation amplifier used to directly monitor 
the load current. However, under high frequency or transient 
conditions, CMR errors would limit accuracy. This ap- 
proach eliminates these problems by gleaning the load 
current from measurements of amplifier supply current. 

The power supply current of one of the bridge op amps is 
measured using ENA117s and 0.2Q. sense resistors con- 
nected to the power supplies. Because the 0.2Q sense resis- 
tor adds negligible resistance error to the 3801cQ input 
resistors of the INA1 17s, no matching resistors are required. 



FIGURE 55. Current-to-voltage converter referenced to the 
negative power supply rail. 



27 



+V S (200V max) 



o.2n> 



INA117 

VvV T T MA- 



— vV\A- 

3 






0.2Q 



'load 



INA117 




-V s (-200V max) JL_ 




10kn 

W\A— ] 



ikn 9kn 



e, 1 




e OUT - l LOAD 



= 5(e, ♦ e 2 ) 



FIGURE 56. Bridge amplifier load current monitor using the INA1 17. 

To understand how the circuit works, notice that since no 
current flows into the inputs of 



4 to 20mA CURRENT LOOP RECEIVER 
WITH to 5V OUTPUT USES THE RCV420 



^LOAD ^1 *2 
If 

R, = R, = R 
Then ' 
e,=I,.R, 



e 2 = -I : • R, 
and 

e i + e 2 = ^OAD * R 

fier with a gain of 5 (the accurate matching of the two 25kft 
input resistors makes a very accurate summing amplifier). 

Then 

e = 5(e, + eg = 5(I L0AD • R), 
since 

R = 0.2ft, 

e o = I L o.,o[lV/A] 



The RCV420 is a current-to-voltage converter designed spe- 
cifically for conversion of 4-20mA input currents into 0-5V 
outputs. A pair of precision 75£2 sense resistors are provided 
internally allowing both inverting and noninverting transfer 
functions. Input common mode signals up to ±40V can be 
accommodated due to the internal 4/1 input attenuator. Also, 
the precision 10.0V reference used for span offseting is 
available to the user. 

Figure 57 shows a typical application. For more details and 
applications, request product data sheet PDS-837. 

VIRTUAL GROUND 

CURRENT-TO-VOLTAGE CONVERTER 

When current-to-voltage conversion with no voltage burden 
is needed, use the transimpedance amplifier Figures 58 — 61. 
In this circuit, an op amp drives the current input node to 
virtual ground by forcing a current equal to I, N through the 
feedback resistor, R FB . Notice that the transfer function is 
inverted: 



V = -I 

OUT X IN 



R FB 




© 



4-20mA 



NOTE: (1) May Connect to Gnd or up to ±40V. 



FIGURE 57. 4-20mA current loop receiver using the RCV420. 




FIGURE 58. Virtual ground current-to-voltage converter. 




FIGURE 59. Virtual ground current-to-voltage converter 
redrawn to Illustrate phase delay due to input 
capacitance and feedback resistor. 



The feedback capacitor, C FB , may be needed for circuit 
stability. To see why, consider the redrawn circuit, Figure 
59. C, N represents the input capacitance of the circuit and in- 
cludes input source capacitance, and op amp input capaci- 
tance. Notice that R FB and C IN form a single pole filter in the 
feedback path to the op amp input. Phase delay through this 
circuit subtracts from the op amp phase margin which may 
result in instability, especially with the large values of R FB 
often used in these circuits. If C FB > C IN , the phase delay will 
be less than 20° assuring stability with most unity-gain- 
stable amplifiers. 

PHOTODIODE AMPLIFIER USING 
VIRTUAL GROUND l/V CONVERTER 

The photodiode amplifier shown in Figure 60 is a common 
application of the transimpedance (current-to-voltage) am- 
plifier. In this application, the shunt capacitance of the 
photodiode reacting with the relatively large feedback resis- 
tor creates excess noise gain. The lpF feedback capacitor 



minimizes the peaking and improves stability as discussed 
previously. Capacitors with the small values often required 
may be difficult to obtain. By using a capacitor divider 
circuit shown in Figure 60A, a larger value capacitor can be 
used. In this example, the lOpF capacitor, C,, is reduced to 
an effective value of lpF by the R 4 , R 5 10/1 divider. The 
lOOpF capacitor, C 3 , keeps the impedance of the divider low 
beyond the C,, R 4 II R 5 zero to maintain C,'s effect. It also 
produces a second-order (40dB/decade) roll-off approxi- 
mately one decade beyond the C/10, R 2 pole. 

The addition of two passive components to the standard 
configuration as shown in Figure 61 introduces a second 
pole that significantly reduces noise. The modification also 
has other advantages. 

The added pole of the improved circuit is formed with R 3 
and C_. Because the pole is placed within the feedback loop, 
the amplifier maintains its low output impedance. If the pole 
were placed outside the feedback loop, an additional buffer 
would be required. The extra buffer would add additional 
noise and DC error. 




C D = 25pF 



E D = I, • 10MQ 



29 



FIGURE 60. Standard transimpedance photodiode amplifier. 



r 



?0pF lOOpF 

HI — r — II— I 



RJ1kQ R 5 100kQ 

— w • 



If 

Photodiode L T 




FIGURE 60A. Standard 



« Amplifier with 
capacitor divider and added feedback pole. 








E o =l,.10Mn — 



FIGURE 61. Improved transimpedance 
fier. 

The signal bandwidth of both circuits is 16kHz: 
1 

[Hz] -» standard circuit 



f- MB =- 



2'TfRj'C, 

1 



1/2 



[Hz]-+ improved circuit 



2 • 7t • (R, • C, • R 3 • C,) 

Where, for the improved circuit: 
C, • R 2 = 2(C 2 • R 3 ) 
and R 2 » R 3 



In the standard circuit, a single 16kHz pole is formed by the 
lpF capacitance in the feedback loop. The improved circuit 



exhibits two pole response. With Cj • R 2 = 2 • C 2 • R,, the 
transfer function is two pole Butterworth (maximally flat in 
the passband). Figure 62 shows the transimpedance fre- 
quency response of the two circuits. At DC, the gain is 
140dB or 10V/(iA. The frequency response of both circuits 
is 3dB down at 16kHz. The conventional circuit rolls off at 
20dB/decade, while the improved circuit rolls off at 40dB/ 
decade. 



PHOTODIODE AMP SIGNAL RESPONSE 





143 




137 


CO 


131 


•D 


I 


125 




119 




113 

































































































Standa 


























































I 


Tip 


rovec 






























Circuit \ 







































































\ 






































































i 



10 100 1k 10k 

Frequency (Hz) 



100k 



FIGURE 62. Transimpedance signal response of standard 
and improved photodiode amplifier. 

Figure 63 shows the noise gain of both circuits. The noise 
problem is due to the noise gain zero formed by the relatively 
high photodiode shunt capacitance, C Q , reacting with the 
high 10MQ feedback resistor. The noise zero occurs at: 



(R,+R 3 ) 



~ 673Hz in this example. 

2 • it • Rj • R 3 • (C + C,) 

Both curves show peaking in the noise gain at about 673Hz 
due to the zero formed by the photodiode shunt capacitance. 
The added pole of the improved circuit rolls off the noise 
gain at a lower frequency, which reduces the noise above 
20kHz. Since the signal bandwidth is 16kHz, the region of 
the spectrum above 20kHz contains only noise, not signal. 
With the values show, the improved circuit has 3 times less 
noise. With the OPA602 (voltage noise = 12nV/VHz), and 
including resistor noise, the improved circuit has 1Hz to 
100MHz noise of 68u.Vrms vs 205u,Vrms for the standard 
circuit. 



PHOTODIODE AMP NOISE GAIN 



50 



10 



-30 



o - 70 



-110 



-1 50 



























































































Standa 












































































































































Ci 


P r 

ci 


ov 
it 


pH 











































































































































































































































10 100 



1k 10k 100k 
Frequency (Hz) 



1M 10M 100M 



FIGURE 63. Noise gain of standard and improved 
photodiode amplifier. 

Another advantage of the improved circuit is its ability to 
drive capacitive loads. Since the output of the circuit is 
connected to a large capacitor, C„ driving a little extra 
capacitance presents no stability problems. Although the 
circuit has low DC impedance, the AC transfer function is 
affected by load. With reasonable loads, the effect is mini- 
mal. With the values shown, a load of 10k£2 in parallel with 
lOOpF has little effect on circuit response. 

For applications where the photodiode can be floated con- 
sider the noninverting I/V converter shown in Figures 64 
and 65. Notice that the buffer amplifier forces zero volts 
across the photodiode as in the conventional transimpedance 
amplifier configuration. 

FET input amplifiers are commonly used for photodiode 
amplifier applications because of their low input bias cur- 
rents. However, FET amplifier bias currents increase dra- 
matically at high temperatures (doubling approximately every 
8 to 10°C). Seemingly small input bias currents at 25°C can 
become intolerable at high temperature. An amplifier with 
only lpA bias current at 25°C could have nearly 6nA bias 
current at 125°C. 

The difference between input bias currents, offset curent, is 
often much better than the absolute bias current. The typical 
bias current of an OPA156, for example, is 30pA, while its 
offset current is 3pA. 

If amplifier bias current is a problem consider the circuit 
shown in Figure 66. The added bias current cancellation 
resistor R, cancels the effect of matching op amp input bias 
currents. This can provide a ten-to-one or better improve- 
ment in performance since voltage offset is due only to I os 
(offset current) reacting with 5MQ. 

A word of caution. Many amplifiers, especially bipolar input 
amplifiers, achieve low bias current with internal bias cur- 
rent cancellation circuitry. There may be little or no differ- 
ence between their I B and I os . In this case external bias 
current cancellation will not improve performance. 



H> — 



Photodiode 





FIGURE 64. 



H> — 



Photodiode 





R 2 



R EQ u,v = R , d+RJ + R, 



FIGURE 65. 



FIGURES 64 and 65. Photodiode amplifier using floating 
virtual ground current-to-voltage 
converter. 




1 



R 2 5MQ > =p C 2 2pF 



J 



FIGURE 66. Differential Photodiode Transimpedance 
Amplifier gives bias current cancellation. 



GLOSSARY 

ABBREVIATIONS, DEFINITIONS 

Bidirectional Current Source — A floating current source 
that provides a constant current independent of the polarity 
of applied voltage bias. 

Current Source — This may be a general term for any 
current source, current sink, or floating current source. In this 
text it usually refers to a current generating device referenced 
to a positive fixed potential such as +V S of a power supply. 
The load must be connected between the current source and 
a more negative potential. 

Current Sink — Current generating device referenced to a 
negative fixed potential such as -V s of a power supply. The 
load must be connected between the current sink and a more 
positive potential. 

Difet® — Burr-Brown's trademark for an integrated circuit 
process which uses dielectric (DI) instead of reverse biased 
junctions (JI) to isolate devices. This technique eliminates 
the substrate leakage inherent in JI processes. The result is 
lower input bias currents for FET input amplifiers, and po- 
tential for higher temperature operation and radiation hard- 
ness. 

Floating Current Source — A current generating device 
with both ends uncommitted. The load may be connected to 
either end, or a floating current source may be connected ar- 
bitrary between two loads. The current sources in the REF200 
are floating current sources. A floating current source may 
require external power supplies. The floating current sources 
in the REF200 are self powered, and require no external 
power supply. 

IA — Instrumentation Amplifier. An IA is not an op amp. 
Unlike an op amp, an IA amplifies the signal at its inputs by 



a fixed gain while rejecting the common mode signal. An op 
amp amplifies the signal at its inputs by its open loop gain 
(ideally infinity). An op amp therefore requires feedback 
components to make a useful amplifier. It normally takes 
three op amps and seven precision resistors to make an LA. 

I B — Bias current. The DC current that flows into or out of the 
input terminals of an amplifier. 

IC — Integrated circuit. Often implies monolithic integrated 
circuit, which is a single-chip electronic circuit. 

I os — Offset current. The difference in I B of the two inputs of 
an amplifier. 

Op Amp — Operational amplifier. An operational amplifier 
is a very high gain direct current amplifier with differential 
inputs. It is intended for applications where the transfer 
function is determined by external feedback components. 

RTD — Resistor Temperature Device. A precision tempera- 
ture transducer using platinum as the active element. Values 
at 0°C of 100S2, 500Q, and 1000Q are standard. Due to the 
high cost of platinum lkQ RTDs are becoming more popu- 
lar. 

TCR — Temperature coefficient of resistance. The change of 
DC resistance with temperature of a resistor. Usually ex- 
pressed in parts per million per °C [ppm/°C]. 

TCR Tracking — The match or tracking over temperature of 
the TCR of two or more resistors. 

Transconductance Amplifier — A voltage to current con- 
verter. 

Transimpedance Amplifier — A current to voltage con- 
verter. 



CLASSICAL OP AMP OR CURRENT>EEDBACK OpTKIF? 

THIS COMPOSITE OP AMP GIVES YOU 
THE BEST OF BOTH WORLDS 



33 



", Tony 



, and R. Mark Stitt (602) 746-7445 



Classical op amps such as the OPA627 have excellent 
performance in applications where the required gain band- 
width is low compared to the gain-bandwidth product of the 
op amp. However, increasing closed-loop gain decreases the 
error-reducing loop gain. Furthermore, starting at relatively 
low frequencies, the loop gain rolls-off at 20dB/decade of 
signal frequency increase. In combination these effects can 
produce significant errors, especially at higher frequencies 
where the loop gain can be very low. 

Current-feedback op amps, such as the OPA603, have good 
dynamic performance at both low and high gains. This is 
because the feedback components set both closed-loop gain 
and open-loop gain, making loop gain and dynamic per- 
formance relatively independent of closed-loop gain. Unfor- 
tunately, the DC performance (V QS , dV QS /dT, CMR, etc) of 
current feedback amplifiers is poor compared to classical op 
amps. 



A composite amplifier using a classical amplifier and the 
OPA603 current-feedback amplifier can combine the best 
qualities of both amplifiers. 

Figures 1 and 2 show noninverting and inverting composite 
amplifiers. Table I shows suggested component values for 
selected gains and measured performance results. 

DC performance of the composite amplifier is excellent. 
Since the OPA603 is in the feedback of the OPA627, the 
composite amplifier retains the excellent DC characteristics 
of the OPA627. In fact, since the OPA627 does not drive the 
load directly, its DC accuracy can be better than the OPA627 
alone. Thermal feedback within an amplifier driving large 
loads will cause errors due to internal thermal gradients and 
package self-heating. The composite amplifier with an 
OPA603 can drive 150Q loads to +10V with no thermal 
feedback to the OPA627. 



IT 




v OUT 




'OUT 

Vout — V, N (FVR,) 



FIGURE 1. Composite Noninverting Amplifier with Preci- 
sion of OPA627 and Speed of OPA603. 



2. Composite Inverting Amplifier with Precision of 
OPA627 and Speed of OPA603. 



OVERALL 






OPA603 










SLEW 


SETTLING 


SETTLING 


GAIN 


GBW 




GAIN 


R,<" 






R. 


RATE 


(0.1%)<*> 


(0.01 %)« 


[V/V] 


[Hz] 


A, 


[V/V] 


["] 


["1 






rv/ns] 


[ns] 


[ns] 


5 


90M 


OPA627 


3 


255 


1020 


499 


1020 


100 


265 


520 


10 


180M 


OPA627 


6 


110 


1000 


200 


1020 


240 


240 


500 


20 


330M 


OPA627 


12 


52.3 


1000 


93.1 


1020 


620 


200 


520 


50 


750M 


OPA627 


26 


49.9 


2430 


40.2 


1020 


730 


320 


530 


100 


1.5G 


OPA627 


52 


49.9 


4990 


20 


1020 


730 


330 


(31 


200 


2.5G 


OPA637 


18 


49.9 


10k 


60.4 


1020 


580 


350 


(3> 


500 


6.0G 


OPA637 


42 


49.9 


25k 


24.3 


1020 


590 


580 


Ol 


1000 


10.0G 


OPA637 


85 


49.9 


50k 


12.1 


1020 


510 


640 


(31 



0) 

E 

3 



0) 



ffi 

c 
o 

(0 

o 

Q. 
< 



NOTES: (1 ) R, shown is for noninverting composite amplifier. For inverting amplifier, R, 
0.01% at this gain. (4) For intermediate gains, use the higher value R . 



= Gain/R 2 . (2) Settling time for 10V output step. (3) Output noise exceeds 



TABLE I. Measured Results for Selected Composite-Amplifier Examples. 



1 990 Burr-Brown Corporation 



AB-007A 



Printed in U.i 



The gain of the composite amplifier is set by R, and R 2 
alone. Errors due to R 3 and R 4 do not affect the gain of the 
composite amplifier. The gain of the second amplifier, set by 
R 3 and R 4 , should be within +5% to assure expected dynamic 
performance. 

Slew rate and full-power response of the classical amplifier 
are boosted in the composite amplifier. Since the OPA603 
adds gain at the output of the OPA627, the slew rate of the 
OPA627 is increased by the gain of the OPA603. For 
example, in the gain-of-100 composite amplifier, the slew 
rate and full-power response of the OPA627 is increased 
from 40V/u.s min (600kHz) to over 700V/(is (1 1MHz). 

Settling time of the classical amp is preserved, even at 
higher gains. Settling time of a classical op amp is limited by 
the time needed to slew to its final value plus the time for its 
internal circuitry to settle to the desired accuracy. Settling 
time for a classical op amp is no better than predicted by a 
single-pole response: 

In (100/%) 
is = — 

2 • Jt • luGBW 

Where: 

T s = Settling time [us] 

f U0BW = Amplifier unity-gain bandwidth [MHz] 
ln(100/%) = Number of time constants needed to settle to 
desired accuracy, e.g: 



ACCURACY 

(%) 


BITS 
(TO 1/2LSB) 


NUMBER OF 
TIME CONSTANTS 


1.0% 


6 


4.6 


0.1% 


9 


6.9 


0.01% 


12 


9.2 


0.0008% 


16 


11.7 



TABLE II. 



The bandwidth of a classical op amp decreases with increas- 
ing closed loop gain. In a gain of 100V/V, the bandwidth of 
the OPA627 decreases from 16MHz to 160kHz. The 0.1% 
settling time therefore can be no better than that of a 160kHz 
single pole system, or 6.9p.s. In the composite amplifier, 
with the OPA603 in a gain of 52V/V, the OPA627 operates 
in a loop gain of 2 V/V resulting in a measured 0. 1 % settling 
time of 330ns. 

Care must be taken when selecting the feedback amplifier, 
A 2 , used in the composite. Excessive phase shift through \ 
will cause instability. The OPA603 has sufficient bandwidth 
to ensure stability when used with amplifiers as fast as the 
OPA627 (16MHz). 

If the bandwidth and settling time advantages of the com- 
posite amplifier are needed, but not the slew rate boost, it is 
possible to make a composite amplifier using a dual op amp 
such as the OPA2107 as shown in Figures 3 and 4. It is best 
to use a dual op amp because of the inherent matching of 
dynamic characteristics. To ensure stability and the best 
transient response, set the gain of A, two times the gain of 



A 2 using the following relationship: 

Gain = 1 + (R 2 /R,) nonin verting 
Gain = -(Rj/R,) inverting 
R 4 = lOkQ 

For Figures 3 and 4, 

Rj _ R4 

a/R2/(2-Ri))-1 

For example, if Gain = 100, R 4 = 10k£2, and R 3 = 1.65k£l 

Cascading two gain stages (each with a gain of 10V/V) would 
give an overall transfer function of 100 V/V and slightly better 
settling time, but the gain would depend on the accuracy of R 3 
and R 4 in addition to R, and Rj. The table below shows pre- 
dicted 0.01% settling time for the three cases. 



CONFIGURATION 


SETTLING TIME 
TO 0.01% 


Single Amplifier 
Composite Amplifier 
Cascaded Amplifier 


20us 
4.6us 
4.1 us 1 ' 1 


NOTE: (1 ) For cascaded amplifier stages, the combined settling time is the 
square root of the sum of the squares of the individual settling times. 



TABLE IB. Predicted Settling Time for Gain-of-100 Ampli- 
fiers Using OPA2107 Dual Op Amp (Unity 
Gain Bandwidth = 5MHz). 




FIGURE 3. Composite Noninverting Amplifier Using Dual 
Op Amp Settles Fast. 




-V, N (rVR,) 



FIGURE 4. Composite Inverting Amplifier Using Dual Op 
Amp Settles Fast. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR - BROWN 




APPLICATION BULLETIN 

• Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



35 



FEEDBACK PLOTS DEFINE OP 



By Jerald G. Graeme (602) 746-7412 



(Originally published in EDN magazine as "Feedback Plots 
Offer Insight into Operational Amplifiers" and "Bode Plots 
Enhance Feedback Analysis of Operational Amplifiers" on 
1 119189 and 212189, respectively.) 

Feedback plots simplify the analysis of an op amp's closed- 
loop AC performance by showing bandwidth and stability 
conditions as a function of the op amp's gain and phase 
response. These plots also provide insight into noise perfor- 
mance and the special feedback requirements of circuits 
such as integrating converters, photodiode amplifiers, com- 
posite amplifiers and active feedback circuits. 

Engineers routinely use Bode plots (1) to determine the 
bandwidth and frequency stability of voltage-gain op amp 
circuits. A Bode plot provides a visual representation of an 
op amp's transfer response and its potential stability. More- 
over, such plots define the circuit's pole and zero locations 
at the intercepts of the response-curve extensions. 

The Bode plot of Figure 1, for example, shows the interac- 
tion of the magnitude response of the open-loop gain (IAI) 
and the reciprocal of the feedback factor (1/P). The fraction 
of the output that feeds back to the input is p. The voltage- 
divider action of Figure l's feedback network determines 
the value of P; for moderate resistance values, 
P = R]/(Ri + R2). For this noninverting example, the feed- 
back equation, Ac L = A/(l + AP), defines the closed-loop 
voltage gain. AP is the loop gain, and where it is high: 

A CL - 1/P = (Ri + R2)/Ri 
AP represents the amplifier gain available to maintain the 
ideal closed-loop response. At the point where the loop gain 
no longer matches the feedback demand, the closed-loop 
curve deviates from the ideal. The Bode plot graphically 
defines this limit by plotting the 1/p curve with the gain- 
magnitude response curve of the op amp. Because the 1/P 
line represents the feedback demand, closed-loop require- 
ments will be satisfied as long as this line is below the 
amplifier-gain curve. Where this condition is no longer true, 
the actual response drops, following the amplifier's open- 
loop response downward. The rate of descent for the roll-off 
is -20dB/decade (for most op amps) and is characteristic of 
a single-pole response. In Figure 1, the heavier line on the 
gain-magnitude plot depicts the resulting closed-loop curve. 

INTERCEPT DEFINES BANDWIDTH 

For a basic voltage-gain amplifier, the location of the f p pole 
determines the closed-loop bandwidth. In this case, a single- 
pole roll-off determines the point at which the gain magni- 
tude goes below 3dB (equivalent to 0.707 of its low-fre- 




-oe, 



ej_ 1/p 
°- ' e, " 1 + 1/A B 



LOG |A| 



R, + R 2 



3dBBW 
Acl\ J 1/P 




-20dB/DECADE 
/ 



LOG f 



LOG f 




FIGURE 1. This feedback analysis provides a summary of 
loop conditions in the 1/P curve and defines the 
underlying poles, zeros, and phase shift. 



quency level). To find this point relative to the Bode plots, 
rewrite the closed-loop gain as 

Ac L = (l/p)/(l/Ap + 1) 

The bandwidth-defining gain error is a result of the 1/AP 
term in the denominator. Because P is constant for the circuit 
in Figure 1, the amplifier gain (A) determines the frequency 
dependence of the loop gain. For a typical op amp, the gain- 



8 

<D 
SI 

E 

3 



3 
CQ 

c 
o 

% 

o 

Q. 
Q. 
< 



e 1991 Burr-Brown Corporation 



AB-028A 



Printed in U.S.A. June, 1991 



bandwidth product is constant after the first break frequency 
occurs and A = jf^f = jlAI where f c is the amplifier's unity- 
gain crossover frequency. For this common condition, 

A CL = 0/P)/0 + 1/0'IAIP) 

The bandwidth is defined in terms of the absolute value 
(magnitude) of Ac L : 

IA CL I = (l/p)/V(l + 1/(1 AI 2 P 2 )) 

which, at the -3dB point, becomes 

IA CL l=0.707(l/p) = (l/pW2 

Comparing the last two expressions, you can see that the 
-3dB bandwidth occurs when IAI = 1/p. This equality is true 
when the gain supply drops to the exact level of the feedback 
demand. When you plot these two functions on the same 
graph, they reach equality at the intersection of the two 
curves. This intercept pinpoints the closed-loop pole loca- 
tion and defines the circuit bandwidth for the voltage-gain 
amplifier. 

STABILITY PREDICTED FROM THE INTERCEPT 

This critical intercept point also exhibits other characteris- 
tics that can help you define conditions for frequency stabil- 
ity. By relating the phase shift to the slopes of the gain- 
magnitude and 1/p curves, you can determine the loop phase 
shift at this intercept. Again, the importance of the intercept 
is apparent from the closed-loop-gain expression, 
Acl = A/(l + Ap). If AP becomes -1, the closed-loop gain 
will be infinite and will support an output signal even in the 
absence of an input signal, which is a condition for oscilla- 
tion. The magnitude of A(3 is unity only at the intercept point 
because it is at this point that A = 1/(3; a negative polarity for 
AP only requires 180° phase shift. 

Virtually every practical analog circuit is a minimum-phase 
system. For such systems, which have only left-half-plane 
poles and zeros, you can directly read the phase shift from 
the gain-magnitude response' 2 '. Although many op amps do 
have a right-plane zero caused by Miller phase compensa- 
tion, the effects of this zero are suppressed below the unity- 
gain crossover. For the case of a minimum-phase system, a 
pole creates a -20dB/decade response roll-off and a -90° 
phase shift; a zero produces the same effects but with 
opposite polarities. Additional poles and zeros simply add to 
the response slope and phase shift in increments of the same 
magnitude. 

Relying on the feedback phase shift's correlation with the 
response slope, you can determine its value at the critical 
intercept from the gain-magnitude and 1/P curves. For the 
example of Figure 1 , the gain-magnitude curve has a slope 
of -20dB/decade and the 1/P curve has a zero slope for a net 
90° feedback phase shift at the intercept. This situation 
leaves a phase margin of 90° out of the 180° that would 
cause oscillation. Because the intercept is well removed 
from the open-loop-response break frequencies, the analysis 
of this example is easier to understand. The intercept occurs 
after the amplifier's first pole develops the full 90° phase 
shift, but well before the second pole has any effect. 



APPROXIMATING PHASE MARGIN 

In cases where the intercept is less than one decade from a 
response break, the Bode approximation of the phase shift 
shows a linear slope that has a maximum error of 5.7° (1) . For 
Figure 1, the phase-shift approximation starts at 0° one 
decade before the break frequency f . From there, it in- 
creases linearly on the log scale to 45° at the break frequency 
and then to 90° one decade above it. 

Using this approximation, you can combine the stability 
criteria for loop-gain magnitude and feedback phase shift to 
obtain the rate-of-closure indicator. Rather than computing 
phase shifts from slopes, you can use this indicator to deal 
with the slopes directly. Rate-of-closure is simply the differ- 
ence in slopes of the gain-magnitude curve and the 1/P curve 
when they intercept. This difference reflects the combined 
phase shift around the feedback loop. For Figure 1, the rate- 
of-closure is 20dB/decade, which corresponds to a stable 
90° phase shift. 

In other cases, the slope of the 1/P curve is not zero, giving 
a 40dB/decade rate-of-closure that indicates an oscillatory 
180° of phase shift. Rate-of-closure alone is an exact stabil- 
ity indicator where the intercept is at least one decade away 
from all other break frequencies. In still other cases, the 
Bode phase approximation modifies the rate-of-closure re- 
sult. 

FEEDBACK FACTOR IS A 
VOLTAGE DIVIDER RATIO 

To use feedback relationships to perform circuit analysis, 
you should consider the feedback network separately. This 
separation parallels the nature of the op amp's open-loop 
gain, which is a characteristic of the amplifier in the absence 
of the feedback network. You only need to retain the loading 
effects between the amplifier and the feedback network to 
determine their individual responses' 2 '. Then, by putting the 
two responses on the same plot, you can see how they will 
work together. 

Figure 2 shows a generalized feedback condition defined by 
Zj and Z 2 . The equations of Figure 2a directly determine the 
circuit response for high loop gain and moderate imped- 
ances. Nonetheless, the input impedance of the amplifier 
alters the simplified results of these equations by shunting 
the feedback network. The inclusion of this loading effect on 
the feedback network completes the 1/P analysis in the cir- 
cuit of Figure 2b. Here, the op amp input resistance (R;), 
differential input capacitance (C jd ), and common-mode in- 
put capacitance (C icm ) all shunt impedance Zj. Except for 
conditions where the feedback impedances have low values, 
you need to include these amplifier characteristics in your 
analysis. 

Where there is impedance in series with the amplifier's 
noninverting input, you must add this too-along with the 
shunting effect of the input's C icm capacitance. You can then 
find the feedback factor from the divider action, ej/e . For the 
1/P curve, this result is inverted and, in the logarithmic 
format of computer simulations, becomes simply 



e, O— 




e — |j e„ 

For |A| » 1/p and Z, » Z, || Z 2 
where Z, - R| || || 



e, O- 



— * — 

LOG1/p = V DB (o)-v DB (j 



37 



FIGURE 2. To determine the 1/p curve for the generalized 
circuit of (a), you can draw a voltage-divider 
circuit that represents the feedback network and 
the. shunting effects of the amplifier input (b). 

V DB (o) - V DB (j). By adding this curve to the plot of the 
amplifier's gain-magnitude response, you can display the 
characteristics of the critical intercept for subsequent feed- 
back interpretation. 

NOISE GAIN AND 1/8 

The 1/p curve also communicates performance information 
across the entire response range of the op amp. For example, 
it displays loop gain, which provides an indication of gain 
accuracy vs frequency and the ultimate bandwidth limit. 
Furthermore, the 1/p curve demonstrates that the circuit's 
signal bandwidth can be different from its noise bandwidth. 
Note that the previous feedback-network analysis returns Z, 
to ground as it would in a noninverting op amp configura- 
tion, even though the op amp shown is in the inverting mode. 

Underlying the difference between noise and signal band- 
width is the concept of noise gain, which is the source of 
some of the more common op amp application 



conditions remain the same. In both cases, your feedback 
analysis is concerned with the gain-error voltage developed 
between the op amp inputs. This error signal always receives 
the gain of the noninverting connection, as you would see if 
you performed superposition analysis. Superposition of the 
signal between the amplifier inputs grounds the signal source, 
producing the noninverting configuration. 

The same condition holds true for the input voltage noise of 
an op amp, resulting in the noise-gain characteristic for the 
1/P curve. In practice, the noise gain and the 1/p curve are 
the same — until they intercept with the gain-magnitude 
curve. After that, the noise gain rolls off with the amplifier 
open-loop response but the 1/P curve continues on its path. 
For the noninverting voltage amplifier, the noise gain and 
the closed-loop gain, Ac L , are the same. 



NOISE BANDWIDTH 



In inverting configurations, this correspondence does not 
hold true, giving rise to frequent surprises during attempts at 
noise filtering. The simplest case of the inverting amplifier, 
where it is common practice to bypass the feedback resistor, 
serves to illustrate the inverting relationship (Figure 3). 
Bypassing the feedback resistor is intended to limit noise 
bandwidth, and it does indeed remove noise presented as an 
input signal. However, the circuit will continue to pass 
amplifier noise across the entire op amp bandwidth. C f 
shunts the signal supplied through Ri for the desired lowpass 
roll-off of the op amp's eje, response. To the op amp noise 
voltage, e n , C f merely presents the unity feedback of a 
voltage-follower. Noise gain drops to unity but continues 
out to the open-loop roll-off of the op amp. This leveling off 
of 1/P also shows why the op amp must be unity-gain stable, 
even though the circuit gain has been rolled off well below 
the amplifier response. With 1/P following the unity gain 
axis, the critical intercept occurs at f c . 

While the continued noise gain is at a lower level, it covers 
much of the amplifier bandwidth, which can result in a 
dramatic increase in output noise. For example, if you're 
using the 2MHz Burr-Brown OPA1 1 1 shown and choose C f 
to obtain a 2kHz roll-off, only 0.1% of the amplifier band- 
width will be enclosed in the intended system response. 
Although the logarithmic scale of the frequency axis may be 
visually deceptive, the remaining 99.9% of the bandwidth is 
still available to the amplifier's voltage noise. For an initial 
gain of 10, the output noise that this amplifier produces is 
more than doubled by the bandwidth effect. Many active- 
filter configurations are subject to the same limitation. 

The only way to avoid excessive noise bandwidth is to 
restrict the frequency range of the op amp. By doing so, the 
control of the noise response switches from the 1/p curve to 
the amplifier roll-off. Where the op amp has provision for 
external phase compensation, this control is a simple matter 
and permits you to remove bandwidth from signal and noise 



alike. However, because most op amps lack an external- 
phase-compensation facility, passive filtering within the 
feedback loop offers a broader solution' 3 '. Such filtering 
introduces a capacitive shunt to ground following the ampli- 
fier but within the feedback loop. 

You can also demonstrate the extended noise bandwidth of 
an integrating converter using a feedback plot but, more 
importantly, the curves illustrate the dynamic-range limit for 
integrator-based instrumentation. In Figure 4, the integrator 
1/P curve also levels off at the unity-gain line for continued 
noise gain out to where the op amp rolls off. Be aware that 
this action has far less noise significance for the integrator 
because of its increasing gain at lower frequencies. Integra- 
tors designed for operation to 1kHz or even higher are 
generally unaffected by the added noise bandwidth. 

Nevertheless, the feedback plot for the integrator demon- 
strates a unique bandwidth limitation involving two critical 



e i o- 



10k£i 



2200pF 
R 2 

-vVV^ 

lookn 




-oe 



■o 



LOG |A| 



1/2it R 2 C, 



NOISE GAIN 




1/0 



LOG f 



CLOSED-LOOP 
RESPONSE " 



CONTINUED 
NOISE GAIN 



FIGURE 3. Highlighting the difference between closed- 
loop gain and noise gain, this inverting op amp 
configuration demonstrates the greater band- 
width that is often available to amplifier noise. 



intercepts. Not only does the 1/P curve intercept the gain- 
magnitude curve at the high-frequency extreme, but it does 
so at the low-frequency end as well. Each intercept indicates 
a lack of amplifier gain for support of the feedback and a 
departure from the ideal response. At the high end, the 1/(3 
curve and noise-gain level off, leaving Ac L to continue as 
long as the loop gain lasts. Next, 1/P intercepts the gain- 
magnitude curve at f c where the noise gain rolls off. 

This intercept is a high-frequency 3dB point for the integra- 
tor response, which then usually rolls up rather than down. 
Upward response in this region is due to signal feedthrough 
caused by the feedback elements in the absence of loop 
control. At the lower frequencies, the increasing gain de- 
mand encounters the DC gain limit of the op amp. This 
intercept marks the second 3dB point for the integrator 
response, which sets the range for accurate performance. 
Both intercepts have a 20dB/decade rate-of-closure, indicat- 
ing stable operation. 



«i O- 



R 

ikO 



1000pF 




-oe 



LOG |A| 



IDEAL 
-RESPONSE 




1/P 



NOISE GAIN 



IDEAL 
RESPONSE 



V 

IAclI 



FIGURE 4. Defining the dynamic range for integrating data 
converters, the integrator 1/p curve displays 
upper and lower intercepts with the gain-mag- 
nitude response. 



Between the two integrator-response limits is the usable 
dynamic range for dual-slope A/D and V/F converters. The 
gain error limits this dynamic range; the plots are a graphic 
representation of this error. The gain error is inversely 
related either to a circuit's loop gain or the difference 
between the amplifier's open-loop gain and the feedback 
demand of 1/p. On the response plots, the loop gain is the 
vertical distance between the two curves. For the Figure 4 
integrator, this separation decreases following 1/Ps en- 
counter with the unity-gain axis. From there, the separation 
finally reduces to zero at f c . The gain error then becomes the 
distance between the dashed continuation of the ideal inte- 
grator response and the actual A CL response. Graphically, 
this distance is the source of the large-signal limitation for 
integrating converters where higher signals correspond to 
the upper frequencies. 

At the other end of the converter range, lower-level signals 
demand low-frequency integrator operation that encounters 
a similar limitation. Below the frequency of the op amp's 
first pole, f Q , the separation between the 1/p and gain-mag- 
nitude curves again drops, signaling reduced loop gain. 
Moving further down in frequency, the 1/p curve finally 
crosses the op amp's DC-gain level, and the actual response 
flattens again. For integrating-type converters, this action 
defines a range of performance that is accurate to within 3dB 
from f c down to the lower intercept. To extend the dynamic 
range, you move the lower intercept downward either with 
a lower integrator-time-constant or with boosted DC gain. 

A higher accuracy dynamic range results from the unique 
loop-gain conditions of the integrator. The loop gain is 
constant for the integrator from f to its unity-gain crossing. 
The gain error in this range is constant as marked by the 
uniform separation of the gain-magnitude and 1/p curves. You 
can compensate for such an error by making a fixed adjust- 
ment to the feedback network, leaving gain-accuracy bounded 
by the stability of the network. This limit permits you to 
adjust the more restricted dynamic range to 0.01% levels. 
For the OPA1 1 1 op amp and a 100kHz integrator crossover 
frequency, this more precise dynamic range has a span of 
100,000:1. 

INPUT CAPACITANCE ALTERS 1/B 

The previous discussion of the inverter and the integrator 
considered the feedback network independent of the ampli- 
fier input shunting. Although engineers frequently use this 
simplification, they often encounter unexpected results. 
Because of the feedback factor, most first-time users of op 
amps with large feedback-resistance values are surprised by 
the response curve. Transient-response ringing or even os- 
cillation sometimes occurs; the common cure is a capacitive 
bypass of the feedback resistor. The 1/p curve can display 
the problem and provide some guidance in the selection of 
the bypass capacitor. 

Underlying the problem is the op amp input capacitance's 
effect on the feedback factor. By including this capacitance 



with the voltage divider formed by the feedback resistors, 
you can achieve the results of the 1/P curve in Figure 5. This 
curve rises at high frequencies, increasing the rate-of-clo- 
sure and flagging the need for closer stability analysis. The 
phase margin drops as 1/P rises and, at the limit, goes to zero 
if the 1/P rise spans one decade of frequency. Generally, the 
span is much smaller than that and the Bode phase approxi- 
mation evaluates the actual conditions. The key to minimiz- 
ing the effect on the feedback factor is the low input 
capacitance that the small input FETs of the OPA128 device 
provide. The net 3pF of input capacitance leaves the re- 
sponse undisturbed until the parallel combination of the two 
resistors reaches 501c£2. 

The capacitive bypassing of R 2 increases the high-frequency 
feedback, which counteracts the shunting of C ia by leveling 
off the 1/P curve. The selection of this capacitor is better 
illustrated by Figure 6's photodiode amplifier. You can 
reduce the non-obvious bandwidth of this application to an 
equation. The circuit contends with diode capacitances at the 
input up to 20,000pF. As a result, the break in the 1/P curve 
is generally far removed from the intercept, making the rate- 
of-closure analysis accurate without requiring any aHinst- 
ment of the phase-shift approximation. 



e i o ^ 

saaka 

! 

3pF i 
I 

I 



|pF 

R 2 

200kn 




-oe 



1 C|H + C fc 



6dB 
OdB 



LOG|A| 



, -20dB/DECADE 

1/P 




LOG f 



5. Higher feedback resistances will react with the 
op amp's input capacitance to produce a peak- 
'hich the 1/P curve anticipates. 



44BH05M 



I 270pF | 4pF 



LOG|A| 



5pF 
Rl 

1MQ 



0PA111 




f^i/aiR^Co + Ci,) 
c, 

BW = 1.4f„ 



= 1/2jtR,f 



-40dB/DECADE 



l-TO-V 
GAIN 




NOISE GAIN 



LOG f 



FIGURE 6. A photodiode amplifier's vokage function serves 
to obscure its bandwidth and stability, but you 
can rely on feedback-loop conditions to define 
its performance. 



Unfortunately, the bandwidth for the circuit of Figure 6 is 
obscured by its function. Because its function is a current-to- 
voltage conversion, rather than simple voltage gain, you 
cannot draw the signal-gain curve on the gain-magnitude 
response to estimate bandwidth. When you inspect the 
circuit to find its bandwidth limitation, you'll see that the 
only inherent break frequency is that of the feedback resis- 
tance and the capacitance of the input circuit. By plotting the 
1/(3 curve, however, you can see that the loop gain remains 
to support the ideal feedback condition far beyond the fj 
break frequency. 

Initially, the 1/(3 curve is flat at unity because of the direct 
output-to-input connection of R f . When the feedback is later 
shunted by C D and C ia , 1/(3 rises at a 20dB/decade rate. The 
transition between these regions occurs at 

fj m 1/2kR,(C d + C ia ) 

where C ia = C id + C icm . 



The intercept with the gain-magnitude curve marks the end 
of the response rise for the noise gain. This curve has a - 
20dB/decade slope so, if left uncompensated, the rate-of- 
closure at the intercept will be 40dB/decade. Thus, the plot 
indicates two poles at that intercept frequency, f p . This in- 
tercept is the point at which there is no longer sufficient 
amplifier gain for the feedback-factor demand, and it indi- 
cates response roll-off independent of the op amp function. 
Any amplifier function would then roll off with a slope equal 
to the rate-of-closure. 

COMPENSATION BREAKS AT THE INTERCEPT 

Because the rate-of-closure is 40dB/decade, you should 
examine phase shift at the intercept to determine the phase 
compensation necessary for stability. When the various 
break frequencies are well removed from the intercept, the 
rate-of-closure accurately reflects 180° of phase shift for the 
uncompensated loop. To avoid oscillation and to achieve 
good damping characteristics, you must reduce this phase 
shift by at least 45° through roll-off of the 1/(3 curve. 

According to the Bode phase approximation, this phase shift 
is the amount of phase introduced at a break frequency. 
Choosing C f to break with R f at the intercept frequency, f p , 
yields 45° of phase margin. Accompanying this phase con- 
dition is a 3dB peak in the signal response, which for a 2- 
pole response pushes the -3dB bandwidth out to 1.4f p . For 
the OPA111 and the feedback elements shown, the 3dB 
response extends to 48kHz. (You can extend this analysis to 
lower capacitance levels, and the common solution men- 
tioned above will still suffice-even for the high-feedback- 
resistance case of Figure 5.) 

As long as C f breaks with R f at the frequency of the inter- 
cept, the 1/(3 rise contributes no more than 45° of phase shift. 
In the range where the op amp phase shift is 90°, this rise 
leaves a stable 45° phase margin. Nevertheless, as the op 
amp approaches its crossover frequency, f c , its contribution 
to phase shift moves toward 135°. The rule of thumb for 
selecting C f remains valid, however, because any intercept 
near f c must be a result of a 1/(3 rise of short duration. The 
added phase shift of the amplifier, accompanied by a neces- 
sary decrease in feedback phase shift at the intercept, results 
in a net zero effect. By simple sketching of the phase 
approximations for the 1/(3 and gain-magnitude curves, you 
can show this transition. 

GEOMETRY DEFINES INTERCEPT 

To select the compensation capacitance, it is desirable to 
reduce the graphical analysis to an equation. Luckily, the 
response plots provide an elegantly simple solution. Straight- 
line extensions of the 1/(3 and gain-magnitude curves form a 
triangle with the horizontal axis. These extensions have 
equal but opposite slopes, which form an isosceles triangle. 
The peak of the triangle, located over the center of its base, 
lies at the average of the base end points. Mathematically, 
this average point is equal to 

Log f p = (Log fj + Log f c )/2 



e,0 




-oe 



LOG |A| 



0° - 




NOISE GAIN 

V 



90° -- 



180° 



i 

I 
I 






1 

1 













LOG f 



FIGURE 7. Although amplifier gain and phase plots sug- 
gest instability, the 1/(3 curve shows stable 
conditions for a circuit with input-lead induc- 
tance. 

Given the expressed logarithmic nature of the frequency 
axis, you can reduce this relationship to the simple geomet- 
ric mean of the two characteristic frequencies: 

where fj = l/27iR^C D + C id + C icm ), and f c equals the unity- 
gain bandwidth of the op amp. 



GAIN AND PHASE CAN BE MISLEADING 

For a third input-circuit effect, the l/($ curve demonstrates 
stable conditions where typical gain and phase plots would 
point to oscillation. In addition to input capacitance, op 
amps have input inductance; this combination produces a 
high-frequency resonance. The inductance is small but ines- 
capable, being associated with internal input wires and being 
compounded by external wiring. 



For very high-frequency amplifiers, like the OPA620 
wideband amplifier of Figure 7, sufficient amplifier gain 
exists at the resonant frequency to give the appearance of 
zero gain margin. A comparison of the output signal (e ) with 
that at the summing junction (ej) produces the plot's gain 
and phase responses. Following unity crossover, the gain 
curve rises again above the unity axis; this rise generally 
guarantees oscillation for lower gain levels. Adding to sta- 
bility concerns is the phase plot, which swings wildly 
through 180° during the gain peak. 

By adding the 1/J3 curve to the plot, you can see that this 
curve does not intersect the gain peak but merely rides over 
it. Without an intercept there is no oscillation, regardless of 
the phase shift, because the loop gain is insufficient. Loop- 
gain demand rises in synchronization with the gain peak 
because the resonant circuit also alters the feedback net- 
work. 

In many cases, the gain peaking results from conditions in 
the amplifier output rather than from the input circuit. In 
such a case, no corresponding modification of feedback 
occurs, and an intercept and oscillation result. However, for 
Figure 7, the gain margin remains high, as you can see by the 
separation between the 1/p curve and the gain response when 
the phase reaches 180°. This separation remains large 
throughout the region of higher phase shift, indicating good 
:ive stability. 



COMPOSITE AMPLIFIERS 

Whereas the normal op amp feedback loop involves only 
one amplifier, designers often need to extend the feedback 
loop to work with composite circuits that use two or more op 
amps for increased gain. By adhering to conventional feed- 
back principles, you can implement phase compensation for 
the extended loop and rely on a Bode plot to provide a visual 
representation of the increased gain and the opportunity for 



For instance, with two op amps in the same loop as in Figure 
8, you can achieve increased gain without incurring any 
added offset and noise error. The input-error effects of the 
second amplifier are divided by the open-loop gain of the 
first amplifier. The net open-loop gain of this composite 
circuit becomes the product of the individual op amp gains 
and greatly reduces the overall gain error and nonlinearity. 

In Figure 8, the two op amps are those of the dual OPA21 1 1, 
which imposes only a modest cost increase over a single 
device. You could, of course, select individual op amps to 
provide specific performance characteristics. In the latter 
case, you might select the input amplifier for good DC and 
noise performance and the output amplifier for its load- 
driving and slewing performance. For example, the output 
amplifier could handle the load current and the resulting 
power dissipation, thus producing no thermal feedback to 
the input of the composite circuit. Moreover, it could also 
fulfill the high-slew-rate demands of the application. The 
input amplifier in this case would only swing through small 
signals. 



R 2 

"VW 1 

iookn 

c, R 4 

Hi — 

0.1 (JF 8WJ 




FIGURE 8. To utilize the boosted gain of the composite 
amplifier, traditional phase-compensation tech- 
niques tailor the gain-magnitude slope to obtain 
a stable region with a 1/P intercept. 

An integrator and a common op amp test loop can demon- 
strate the benefits of using a composite amplifier. By extend- 
ing the composite open-loop gain to higher levels, you can 
expand the dynamic range for integrating analog functions. 
The low-frequency intercept moves back by a factor equal to 
the added amplifier gain. This change is so extreme that 
other error effects will surface well before the gain error 
from the intercepts. For two op amps in the same loop each 
having lOOdB open-loop gain, the composite gain is 200dB. 
At this gain level, an input error of InV will develop the full 
10V output swing. Long before the circuit reaches that limit, 
noise becomes a prime AC constraint and typically restrains 
lower-level accuracy over a dynamic range of about 



3,000,000:1. Nevertheless, this restraint is a 30:1 improve- 
ment over a single op amp and moves the focus of measure- 
ment accuracy to other factors. 

In the op amp test-loop application' 4 ', the addition of the 
second amplifier removes signal swing from the output of 
the tested device. The extra gain transfers that voltage swing 
to an isolated output and removes any gain error from the 
signal detected at the tested amplifier's inputs. This gain- 
error removal permits the discernment of other input-error 
signals for the measurement of parameters such as power- 
supply and common-mode rejection. If these parameters 
were to approach the level of the amplifier's open-loop gain, 
gain-error signals at the input would cloud the effects of the 
measured parameter. 

PHASE COMPENSATION 

FOR THE COMPOSITE AMPLIFIER 

With a composite op amp structure, you must include the 
roll-off characteristics of both amplifiers in your AC analy- 
sis and have some means of providing phase compensation 
for the loop. Two op amps in a common loop invite oscilla- 
tion; the individual amplifier poles combine for a composite 
2-pole roll-off. As shown in Figure 8, the logarithmic scale 
makes the initial composite-response curve the linear sum of 
the two individual responses. The upper, dashed response 
curve, which has a -40dB/decade slope, shows this result. 

Two methods are available for compensating the composite 
loop. One modifies the gain-magnitude response and the 
other alters the 1/|3 curve. The more usual of the two ap- 
proaches is to reduce the slope of the gain-magnitude curve 
in the vicinity of the intercept, as Figure 8 does. After 
forcing the compensated response to roll off earlier, the 
gain-magnitude curve returns with a more gentle slope to the 
boundary of the uncompensated response. This action serves 
the general-purpose requirements of voltage-gain applica- 
tions and produces a stable range that you can place almost 
anywhere in the total composite-gain range. 

Figure 8 achieves this compensation by creating a modified 
integrator response for IC 1B . Because this integrator is an 
inverting circuit, the inputs of IC 1A are reversed to retain 
only one phase inversion in the loop. Capacitor Q blocks the 
local DC feedback, and the overall gain is still the product 
of the two open-loop gains. The integrator response that R 3 
and C] established for IC IB rolls off this composite gain. 
Next, the first open-loop pole of ICi A returns the compen- 
sated response slope to -40dB/decade. At a higher fre- 
quency, a response zero provides the region of reduced slope 
thanks to the inclusion of R 4 . Above the break frequency of 
R4 and C], R4 transforms the response of IC 1B from an in- 
tegrator to an inverting amplifier with a gain of -R^. 

Where this gain is unity, the compensated response drops to 
and follows the open-loop response of IC 1A as shown. For 
gain levels other than unity, you have different options, 
which you can explore by using other response plots and 
defining the particular stable conditions you have in mind. 



Having control of this gain becomes particularly useful as 
the 1/p intercept approaches the uncompensated unity-gain 
crossover point. In this region, the second poles of the two 
op amps increase the phase shift. In such cases, you have to 
make the magnitude of the internal R4/R3 gain less than unity 
to force the compensated response to cross over earlier. 
Generally, when you have two op amps of the same type, 
making R 4 = R3/3 will yield a unity-gain stable composite 
amplifier. 

The net phase correction that you can achieve with this 
technique depends on the frequency-response range for 
which you maintain the -20dB/decade slope. This span 
begins with the R4Q break frequency and ends with the 
intercept of the composite open-loop response. After this 
intercept, the lack of open-loop gain returns the response to 
that of the uncompensated composite amplifier. To ensure a 
phase margin of 45° or more, you can use the guidance that 
the Bode phase approximation provides; the plot shows that 
this reduced slope region must last for three decades of 
frequency and must intercept the 1/p curve after running for 
at least a decade. 

COMPOSITE AMPLIFIERS EXTEND BANDWIDTH 

Although most engineers are familiar with this type of phase 
compensation, it is too restrictive of bandwidth at higher 
gains. For applications requiring higher gains, you can 
greatly extend the bandwidth and reduce the settling time by 
40:1 by using a different phase-compensation technique. 
The general-purpose R4 = R 3 case of Figure 8 sets a constant 
closed-loop gain-bandwidth product. Looking at the curves, 
you can see that the closed-loop bandwidth is the same as 
that for IC JA itself when BW = f p = fJ/^c L . Even so, the large 
separation between the compensated and uncompensated 
responses shows a significant sacrifice in bandwidth — ex- 
pressly for the accommodation of phase compensation. 
Uncompensated, the gain-magnitude response has a gain- 
bandwidth product that increases with closed-lo op ga in and 
that provides a potential bandwidth of f p = fJ^A^i. Com- 
paring the last two expressions shows that the potential for 
bandwidth improvement equals VAc L , which is significant at 
higher gains. 

COMPENSATE THE 1/B CURVE 

You can take advantage of quite a bit of this bandwidth- 
improvement opportunity by compensating the 1/P curve 
instead of the gain-magnitude response curve. By referring 
back to the rate-of-closure stability criteria discussed previ- 
ously, you would see that both curves contribute to the rate- 
of-closure parameter even though the gain-magnitude curve 
is generally the focus of phase-compensation efforts. To 
satisfy the rate-of-closure criteria, all that is necessary is to 
control the difference between the slopes, regardless of the 
slopes of the individual curves. So, instead of reducing the 
gain-magnitude slope, increase the 1/P slope (Figure 9). A 
simple capacitive bypass of feedback resistor R 2 accomplishes 
this slope increase for a final 20dB/decade rate-of-closure. 







80pF 




SINGLE 
AMPLIFIER 

~'fp = 'AkR 2 C,\ f 



-20dB/DECADE 



LOG f 



FIGURE 9. For greater bandwidth in high-gain circuits, you 
can provide phase compensation for the 1/p 
response to retain a smooth open-loop response 
for fast settling. 

An integrator configuration, on the other hand, with its 
special characteristics, inherently produces the -20dB/de- 
cade slope for 1/p and achieves optimum bandwidth and 
dynamic range. 

Two factors distinguish this feedback-factor compensation 
technique for higher gains. Greater bandwidth is open for 
reclaiming, and the associated 1/p curves are well above the 
unity-gain axis. From higher levels, the 1/P roll-off is de- 
veloped well before its intercept with the gain-magnitude 
curve. Starting this roll-off a decade ahead of the final 
intercept produces a 45° phase adjustment for a like amount 
of phase margin. The slopes of the two curves show that, in 
order to accomplish this phase adjustment, Q must break with 
R 2 one-half decade below the initial intercept frequency, f p . 
Then, the 2:1 difference in slopes will place the new inter- 
cept one-half decade above f p for the required full decade of 
the 1/p roll-off. 



CHOOSING C F FOR THE COMPOSITE AMPLIFIER 

Again, the design equations for the required value of Q and 
the resulting bandwidth are obvious from the logarithmic 
nature of the frequency axis. Setting f p ' at one-half decade 
below f p implies that 

Log f p - = (Log f p + Log yi0)/2 

for which f p ' = fp/VlO. From before, you'll remember that f p 
= yVAcL describes the uncompensated curve's bandwidth. 
The compensated bandwidth is 

BW = f p ' = yVdOAaJ 

Here, f c is the unity-gain crossover frequency of the com- 
posite gain-magnitude response. As becomes obvious when 
you examine this expression, the improved bandwidth falls 
short of the total poten tial by VT o. However, it is better than 
the Figure 8 result by ^(AqJIO), or a factor of 10, for a gain 
of 1000. Setting C f to break with R 2 at f p ' defines the value 
of this capacitor as 

C f = V(10A CL )/27tR 2 f c 

For the op amps of the dual OPA2111 shown, the gain-of- 
1000 bandwidth becomes 20kHz as compared with the 2kHz 
you'd realize if you used just one of the op amps. 

COMPOSITE COMPENSATION EFFECTS 

Settling time also improves when you choose the composite 
amplifier's 1/P curve for phase compensation. The improve- 
ment is a result of both the increased bandwidth and the 
retained constant gain-magnitude slope. For a single ampli- 
fier of the OPA21 1 1 type, for a gain of 1000, the settling 
time would be 700|is to 0.01%. Because the Figure 9 
amplifier has 10 times the bandwidth of a single amplifier, 
the settling time drops by the same factor to 70|is. This 
improvement would not be possible without the smooth and 
continuous slope of the compensated-amplifier response. A 
response having an intermediate pole and zero, such as 
Figure 8 does, has low-frequency response terms that are 
slow to settle following a transient. Known as an integrating 
frequency doublet, this pole/zero combination is notorious 
for its poor settling time (5) . By providing phase compensa- 
tion for the 1/P curve, you ensure that the smooth gain- 
magnitude curve is left undisturbed, therefore achieving the 
optimum settling time. 

At lower gains, the benefit of the 1/fJ compensation tech- 
nique diminishes as does its control of phase. Because lower 
gains have 1/(3 curves closer to the unity-gain axis, they have 
less room for 1/P roll-off. To produce an intercept with the 
gain-magnitude curve after a decade of 1/(3 roll-off requires 
a minimum closed-loop gain of 10. Op amp phase shifts 
impose further limits by growing from 90° to 135° as they 
approach the unity-gain crossover frequency. In the practical 
case, this phase-compensation method needs gains of 30 or 
more for good stability. 

This type of phase compensation does have an unusual 
aspect: Too great a compensating capacitance will have a 
surprising effect. Whereas increasing such capacitance nor- 
mally yields more damping and a more stable response, 



making C f too large will cause instability. As C f increases, 
the resulting intercept moves toward f c and encounters the 
added phase shift of the secondary-amplifier poles. Even 
greater values of Cf will drop the 1/|3 curve to its limit at the 
unity-gain axis. From there, it proceeds along the axis to the 
magnitude-curve intercept that guarantees oscillation. Only 
a range of compensation-capacitor values provides stability 
with this second approach; the 1/P curves display this range 
for sensitivity-analysis purposes. Because of the capacitor's 
window of stable values, a random selection of C f followed 
by a stability test is likely to miss the bandwidth opportunity 
of this technique. 

PHASE ONLY MATTERS AT THE INTERCEPT 

Another concept fundamental to op amp feedback in com- 
posite-amplifier circuits becomes apparent when you exam- 
ine phase shift and stability. Composite amplifiers such as 
the one in Figure 10 produce a -40dB/decade slope over 
wide ranges both before and after the 1/p intercept. Because 
this slope corresponds to a 180° phase shift, frequent con- 
cern over stability conditions arises at points other than that 
of the critical intercept. Beyond the 1/P intercept, the loop 
gain is less than 1 and therefore it is easy to see that the 
circuit cannot sustain oscillation. Yet, prior to the intercept, 
the gain of the feedback loop is very high and would seem 
capable of causing the circuit to oscillate. 

In reality, the high loop gain is a protection against, rather 
than a promoter of, oscillation. Sustained oscillation de- 
pends on the op amp's gain-error signal. In Figure 10, the 
gain error, e^A, appears between the op amp inputs and 
receives amplification from the closed-loop gain, A CL . Here, 
A CL is that of the noninverting configuration, the noise gain 
that reacts with any input-referred error signal. To sustain 
oscillation, the amplified error signal must independently 
deliver the output signal. This action requires that (-e /A)A CL 
= e . Note that e appears on both sides of this equation; it 
should therefore be obvious that any solution must conform 
to very specific constraints. This equation expresses both 
polarity and magnitude constraints; the composite amplifier's 
180° phase shift satisfies the sign change. 

For the magnitude constraint, two possible solutions exist. 
The first is e = 0, which is the stable state for the composite 
amplifier in the questioned region. There, the loop gain 
makes the signal eJA too small to independently support an 
output signal. In the plots of Figure 10, cJA starts at a very 
low level due to the high loop gain at low frequencies. As 
you move up in frequency, the gain-error signal rises while 
the amplifier-response slope signals its polarity inversion 
through the 180° phase shift. This inversion increases the 
output signal but cannot sustain it until the gain-error signal 
reaches a sufficient level. This critical level is a prerequisite 
for oscillation. 

This level applies to the second solution for the magnitude 
constraint. At this level, A/A CL has unity magnitude and 
maintains the balance for the previous feedback equation's 
magnitude requirement. Unity loop gain occurs at the 1/P 



R 2 




FIGURE 10. A phase shift of 180° causes oscillation only 
where the gain-error, cJA, is capable of in- 
dependently supporting the output signal. 

intercept where the open-loop and noise-gain curves meet. 
Without phase-compensation intervention, this intercept sat- 
isfies both the phase and magnitude requirements for oscil- 
lation. Beyond this point, e Q and A fall off together, leaving 
the eJA signal constant and unable to support oscillation 
with the reduced gain. At the point where the magnitude of 
the gain error and the feedback phase shift must both reach 
specific levels to support oscillation, the intercept becomes 
critical. Before or after the intercept, the loop phase shift can 
be at any level and the gain-error magnitude will not be 
sufficient to cause instability. 

Unfortunately, despite the composite amplifier's very spe- 
cific requirements for oscillation, the greatly varied applica- 
tions of op amps make this critical condition all to easy to 
encounter. To contend with this problem, you can rely on the 
1/P curve to present a visual prediction of the problem and 
provide insight into a solution. 

ACTIVE FEEDBACK VARIES 1/B 

Some applications demand that you include a second active 
element in the feedback loop to produce a varying feedback 
factor. In these applications, both the magnitude and the 




FIGURE 11. For this common analog divider, a variable 
feedback magnitude allows a range of condi- 
tions that define bandwidth and stability. 



frequency characteristics of 1/fJ become variables. Fortu- 
nately, the gain- and feedback-response curves offer a means 
of quickly evaluating the range of conditions resulting from 
the changing feedback. 

The most common way to provide magnitude variation in 
the feedback factor is to use a low-cost analog divider 
realization. Placing a multiplier in the feedback loop of an 
op amp (Figure 1 1) makes feedback a function of a second 
signal and therefore produces divider operation. With signal 
dependent feedback, the bandwidth and stability conditions 
also become variables. 

Figure 1 1 shows the divider connection 16 ' and demonstrates 
the effect of voltage-controlled feedback on l/p\ The 
amplifier's feedback inverts the function of the multiplier by 
placing the feedback signal under the control of the e 2 signal. 
Then, the multiplier's transfer function of XY/10 delivers 
e o (e2/10) to R 2 . This action scales the feedback signal by 
comparing e 2 to 10V reference level to obtain 

p = ( e2 /10) R,/(R, + R 2 ) 

With the feedback factor under control of this signal, the 
1/(3 curve moves across the full range of the gain-magnitude 
response. As e 2 nears zero, the 1/P curve approaches infinity, 
leaving the op amp essentially in an open-loop configura- 
tion. At the other extreme, a full-scale 10V value for e 2 
delivers a feedback signal to R 2 that equals e almost as if the 
multiplier were not present. Then, the net response is that of 
a simple inverting amplifier with a feedback factor of 
R,/(R, + R 2 ) and an inverting gain of-R^. 



INTERCEPT VARIES WITH 1/B 

Between the extremes, the variation of e 2 moves the l/p 
curve from as low as the unity-gain axis to above the upper 
reaches of the amplifier's gain-magnitude curve. This varia- 
tion moves the critical intercept and requires attention to the 
rate-of-closure over the entire span of the gain-magnitude 
response. If no significant multiplier phase shift exists, the 
feedback will always resemble that of an inverting amplifier 
for a zero l/p slope, and you can ensure stability by just 
using a unity-gain-stable op amp. You can then read the 
range of bandwidth for the divider operation directly from 
the moving l/p intercept. For a given e 2 range, the intercept 
moves linearly with the signal, defining the corresponding 
bandwidth range. 

The multiplier also introduces phase shift that alters the net 
phase shift around the feedback loop. Poles in the response 
of the multiplier circuit are zeros in the inverse l/p function, 
causing the curve to rise at high frequencies. This rise moves 
toward the critical intercept when the multiplier control 
voltage, e 2 , increases. This rise has an impact on the rate-of- 
closure, and the op amp must introduce a dominant pole to 
maintain stability. For the components shown, the OPA1 1 1 
dominates the circuit roll-off because of its 2MHz unity-gain 
crossover frequency. This frequency is well below the 10MHz 
bandwidth of the MPY634 multiplier, placing the op amp in 
control. Other options that use a separate feedback path to 
restrict the op amp bandwidth are also available' 3 '. 

VARIABLE 1/13 FREQUENCY RESPONSES 

Other ways of providing variable feedback are also avail- 
able. For example, you can have the signal control the 
frequency-rather than the magnitude-characteristics of the 
feedback. The result is a variable slope at the intercept, as is 
the case with the voltage-controlled lowpass filter in Figure 
12. The basic elements of the lowpass filter are the op amp, 
the resistors, and the capacitor. If you replace the multiplier 
with a short circuit, these elements form a fixed-frequency 
roll-off. Essentially, this shorted condition is established 
when e 2 = 10V and when the gain through the multiplier is 
unity. Capacitor Q then breaks with R 2 to define the filter 
roll-off just as if the resistor and capacitor were directly in 
parallel. 

For levels of e 2 below full scale, the multiplier serves as a 
voltage-controlled attenuator to effectively alter the filter 
time constant. Attenuating the feedback voltage to R 2 lowers 
the signal current to the summing node, which has the same 
effect as increasing the resistor's value. Increased effective 
resistance corresponds to a decrease in the resistor's break 
frequency with Q. This break defines the variable filter roll- 
off when 

f p = e^OnR^ 

The maneuvering of the l/p curve through this operation 
deserves closer inspection. The circuit exhibits a signal- 
dependent transition between the two different loops, which 
alternately control the feedback. At low frequencies, C } is 
effectively an open circuit, and the controlling feedback path 



R 2 

I MA- 

100k£2 

R, C, 

)l 1 

e < 10kn 1000pF 








NOISE GAIN 



FIGURE 12. In this filter circuit, variations in the fre- 
quency characteristic of l/p make possible a 
changing 1/P slope at the intercept. 

is through the op amp and the multiplier. This composite 
structure has resistive feedback that defines a signal gain of 
-R^i and a noise gain of (R] + R 2 )/Rj. The latter rela- 
tionship equals l/p at low frequencies and the curve of 
interest starts at this level with a zero slope. At the high- 
frequency end, the composite structure is overridden when 
Ci acts as a short circuit, which results in a unity feedback 
factor around the op amp. This short circuit absorbs all 
feedback current from R 2 without any corresponding change 
in the amplifier output voltage. The feedback loop of the 
composite structure is then disabled, switching feedback 
control to just the op amp. With then providing a unity 
feedback factor to the op amp, the l/p curve follows the unity- 
gain axis at high frequencies. 

Once the l/p levels are fixed at the extremes, the multiplier 
determines the nature of the transition between the two. In 
the transition region, feedback currents from R 2 and Q 
compete for control of the summing node of the op amp 
input. The contest for dominance is analogous to the fre- 
quency-dependent control of impedance with a parallel RC 
circuit. In both cases, the 3dB point, where each element 
carries the same magnitude of current, defines the transition 
of control. The Figure 12 filter achieves equal element 
currents when the impedance of C t and the effective im- 
pedance of R 2 are equal. This equality defines the voltage- 



controlled roll-off frequency of the filter as previously 
expressed. At this frequency, 1/p also rolls off and drops at 
-20dB/decade to the high-frequency limit of the unity-gain 
axis. 

RATE-OF-CLOSURE VARIES WITH 1/B 

The stability conditions of the Figure 12 circuit depend on 
the particular feedback loop or the combination of elements 
that are in control at the intercept point. For the lower- 
frequency filter cutoff frequencies illustrated, the op amp's 
bypass capacitor takes control before the intercept and 
defines the relevant feedback conditions. Because the 1/p 
curve follows the unity axis at the upper end, you can 
guarantee stability by ensuring that the op amp be unity-gain 
stable. For higher-frequency cutoff frequencies, the 1/p 
transition moves toward the gain-magnitude curve of the op 
amp. Circuit response cannot move beyond this limit, so the 
op amp roll-off becomes the upper boundary of filter opera- 
tion. 

When the cutoff frequency approaches this boundary, the 
intercept rate-of-closure varies, prompting stability analysis. 
First, the zero of the 1/p curve approaches the intercept, 
where it increases the slope of the curve. Because this action 
reduces the rate-of-closure, stability is improved and a more 
detailed analysis is unnecessary. A continued increase in the 
cutoff frequency moves the 1/p curve further to the right 
where its pole interacts at the intercept. This break frequency 
returns the rate-of-closure to 20dB/decade, thus retaining 
stability. Beyond this point, the intercept occurs at the flat 
lower end of the 1/P curve, and no further change in the rate- 
of-closure takes place. 

Utilizing these various feedback conditions and a unity- 
gain-stable op amp, you can design a composite circuit that 
fulfills its primary stability requirement over the entire 



operating range. In addition, however, you may sometimes 
require a multiplier having a bandwidth much greater than 
that of the op amp, as the two previous examples demon- 
strate. Without a wide-bandwidth multiplier, 1/P would 
begin to rise near the higher-frequency intercepts and in- 
crease the rate-of-closure. The OPA1 1 1 avoids this compli- 
cation when using the MPY634 multiplier by maintaining a 
dominant op amp pole. 

Other applications may involve feedback peaking and op 
amps that are not unity-gain stable-log amps and active 
filters, for example. For these and other variations requiring 
feedback analysis, the test remains the same. Look for the 
critical condition where the rate-of-closure is 40dB/decade. 
Where conditions approach this level, conduct further analy- 
sis and compare phase-compensation alternatives for opti- 
mization. 

REFERENCES 

1. Tobey, G. E., Graeme, J. G., and Huelsman, L. P., 
Operational Amplifiers: Design and Applications, McGraw- 
Hill, 1971. 

2. Bower, J. L., and Schultheis, P. M., Introduction to the 
Design of Servomechanisms, Wiley, 1961. 

3. Stitt, R. M., and Burt, R. E., "Mbglichkeiten zur 
Rauschunter-druckung,"£Mfr0m'£, December 1987, pg 1 12. 

4. Lewis, E. D., "Compensation of Linear IC Test Loops," 
Electronics Test, May, 1979, pg 83. 

5. Dostal, E. J., Operational Amplifiers, Elsevier Scientific 
Publishing, Amsterdam, Holland, 1981. 

6. Wong, Y. J., and Ott, W. E., Function Circuits: Design 
and Applications, McGraw-Hill, New York, NY, 1976. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR - BROWN 




APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



49 



INCREASING INA117 DIFFERENTIAL INPUT RANGE 

By R. Mark Stitt (602) 746-7445 



The INA117 is a monolithic difference amplifier with the 
unique ability to accept up to ±200V common-mode input 
signals while operating on standard ±15V power supplies. 
Because the gain of the INA1 17 is set at 1 V/V, and because 
the output would saturate into the rails at about +12V, the 
maximum specified differential input range is ±10V. 

Since the common-mode input range is +200V, it makes 
sense that some designers would also like to use the part for 
differential inputs greater than ±10V. Figure 1 shows the 
recommended circuit. Adding resistors to the input may 
seem simpler, but there are some problems with that ap- 
proach. 



380kQ 



380k£i 

v 3 °tHW- 



21.1kQ- 




V3-V2 



1 +" 



1 9 R 7 

R 6 



FIGURE 1 . INA 1 1 7 with Increased Differential Input Range. 

The performance of the INA 117 depends on extremely 
precise resistor matching (0.005% for 86dB CMR). Resistors 
added to the input must be adjusted to at least this accuracy 
to maintain high performance. Both gain error and CMR 
must be adjusted. Maintaining 86dB CMR over temperature 
requires lppm/°C resistor TCR tracking. Significant resis- 
tance added external to the INA1 17 would require the same 
performance. 

By using the circuit shown in Figure 1, internal resistor 
matching is preserved, and the INA1 17 CMR and CMR drift 
with temperature are maintained. Gain can be set independ- 



ently of CMR by adjusting the inverter resistors, R 6 , Rj. Gain 
drift is preserved so long as R 6 and R 7 track with temperature. 
Furthermore, noise at the output is improved by the gain 
reduction factor whereas, it is unchanged with the other 
approach. 

To understand how the circuit works, consider the INA1 17 to 
be a four-input summing amplifier as shown in Figure 2. 




V2<>- 



2 



380W2 



R 3 
380kn 

v 3 c> 7f-VW- 



21.1kn 




20.0kH 



INA117 



-0*V n 



6 6 

V, v 5 



*Vout =V 3 "V 2 +19V 5 -18V, 



FIGURE 2. INA1 17 Shown as a Four-Input Summing Am- 
plifier. 

CMR is preserved and the gain is reduced if a small portion 
of the output signal is inverted and fed back to pin 5 with V! 
set to zero (V, grounded). 



Where: V 0UT = V 3 - V 2 + 19 • V 5 - 18 • V, 



If ' V 3 =- V our-iyR6. then 

V - V 3 - V 2 
V OUT 



19 • R 7 

1 + 7 



SELECTED-GAIN EXAMPLES 



GAIN 






(V/V) 


(kO) 


(kn) 


1/2 


1.05 


20.0 


1/4 


3.16 


20.0 


1/5 


4.22 


20.0 



I 

E 

3 



2 
3 

m 

c 
o 

53 

| 

Q. 
Q. 

< 



^1990 Burr-Brown Corporation 



AB-001B 



Primed in U.S.A. March, 1991 



If CMR adjustment is desired, add a 10Q fixed resistor and 
a 20fl pot as shown in Figure 3. Adjust CMR by shorting 
together pins 2 and 3 of the INA1 17 and driving them with 
a 500Hz square wave while observing the output on a scope. 
Using a square wave rather than a sine wave allows the AC 
signal to settle out so that the DC CMR can be seen. The 



CMR trim will change the gain slightly, so trim CMR first, 
then trim gain with R 6 , R ? if desired. 
The INA117 is now available in three standard 8-pin 
packages: hermetic TO-99, plastic DIP, and the small 
surface-mount SOIC package. 



V 2 c- 



R, 

380kQ 



^3 

380kO 



"2 
380kQ 




21.1kf2< <20.0kfl 



-vw- 

-±r 20Q 



INA117 



10£1 



R 7 




Re 



FIGURE 3. INA1 17 with Increased Differential Input Range with CMR Trim. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR - BROWN 




APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



51 



AC COUPLING INSTRUMENTATION AND DIFFERENCE 

FEATURING CIRCUITS FOR: 
INA117±200V DIFFERENCE AMPLIFIER • INA106-BASED ±100V DIFFERENCE AMPLIFIER • 
INA105 AND INA106 G = 1, 10 DIFFERENCE AMPLIFIERS • INA101, INA102, INA103, INA110, INA120 



By R. Mark Stitt (602) 746-7445 



The need to glean AC signals from DC in the presence of 
common-mode noise frequently occurs in signal condition- 
ing applications. AC coupling to an instrumentation ampli- 
fier (I A) or difference amplifier can be used to accurately 
extract the AC signal while rejecting DC and common-mode 
noise. 

Adding capacitors and resistors to AC couple the inputs of 
an instrumentation amplifier or difference amplifier seems 
like an obvious approach for AC coupling, but it has prob- 
lems. The DC restoration circuits shown in this bulletin have 
the same transfer function but without the foibles. 

Common-mode rejection of a difference amplifier depends 
on extremely precise matching of input source impedance. 
Adding RC networks to the inputs of either an IA or a 
difference amplifier can significantly degrade the CMR, 
especially for AC inputs. Even if the CMR is trimmed, 
maintaining performance over temperature can be a prob- 



The DC restoration circuits shown solve this problem by 
placing a low-pass network in the feedback to the reference 
pin of the IA or difference amplifier. The low-pass pole 
translates into a high-pass function as referred to the input 
with f 3dB = Gain/2«TC«R«C. The Gain term refers to the Gain 
from the reference pin to the output of the IA or difference 
amplifier. The selection guide shows this Gain term as the 
"High-pass multiplier". 



v 2 o — MA- 



380ki2 



R 3 
380kQ 



V 30 M/L 



R 5 

21.1k£2 




INA117 



0.47pF 




OPA602 



1MO. 



Vout=V 3 -v 2 



The DC-restored INA117 is shown in Figure 1. With the 
values shown, the high-pass zero is =6.5Hz. 

The INA 1 1 7BM has a CMR of 86dB min. If improved CMR 
is required for the DC restored INA 117, use the circuit 
shown in Figure 2. Since the trim resistors are small, they 
will not degrade the stability or drift performance of the 
INA117. 

The MAI 17 has a common-mode input range and differen- 
tial offset range of up to ±200V. If a lower common-mode 
and differential offset range of ±100V is acceptable, the 
INA 106 can be used for lower noise and twice the small 
signal bandwidth (400kHz vs 200kHz). 



380kil 



380kQ 



R 2 
380kQ 

-vW- 



2i.ikn 




20 a 

CMR 

Trim 



-ion 



0.47(JF 




1MQ 



= V,-V, 



FIGURE 1. AC-Coupled INA117. 



FIGURE 2. AC-Coupled INA1 17 with CMR Trim. 

The simplest circuit for the DC-restored INA106 is shown in 
Figure 3. The INA106 is reversed from its normal Gain-of- 
10 configuration. The lOOkQ, 10k£2 resistors form a 11/1 
voltage divider on the input so that +100V at pins 1 and 5 are 
divided down to less than ±10V at the op amp inputs. The 
R j; R 6 network provides the proper feedback Gain for an 
overall unity-gain transfer function. Since the precise resis- 
tor matching of the INA 106 is disturbed by the R 5 , R 6 
network this circuit requires trims for both CMR and Gain. 



CO 

i— 

<D 

E 



c 



c 
o 

SI 

I 

a 
a 
< 



®1990 Burr-Brown Corporation 



AB-008A 



Printed in U.S.A. August, 1991 



v 5 o- 



R 2 
100kfl 

-MA- 



iookn 
v lC> l|_^yu 



R, 

iokn 




INA106 



R 6 

1.56kQ 



i76n 



500Q 
CM R Trim 
(158Q Norn) 



0.22uF 




OPA602 



R, 

1MQ 



-o 

VOUT 



FIGURE 3. AC-Coupled ±100V Difference Amp Using the 
INA106. 

Furthermore, Gain and CMR adjustments using R 5 R 6 , and 
the 500Q trim pot connected to pin 3 are interactive. The 
excellent CMR stability vs time and temperature of the 
INA106 is preserved since the added trim resistors are small. 

If you want to use the INA106 for a +100V DC-restored 
difference amplifier without any trims, use the circuit shown 
in Figure 4. Gain is set directly by the R 5 , R 6 divider. The 
buffer amplifier, A 2 , presents a low impedance to the feed- 
back resistor in the INA106 to preserve resistor matching 
and CMR. 



When using the DC restored +100V difference amplifier 
shown in Figure 4, no trims are required for good CMR. 
However, the circuit shown in Figure 5 may be used to fine 
trim CMR if desired. Since the added trim resistors are 
small, they will not degrade the stability or drift of the 
INA106. 

DC restoration can be used with any of the standard IAs 
shown in the table using the same technique as shown in 
Figure 6. Since all of these IAs use unity-Gain difference 
amplifiers, the high-pass multiplier is unity. 



100kfi 




INA106 



OPA2107 




1.13kQ 



0.22uF 




1/2 
OPA2107 



R, 

1MQ 



-O 

Vout- 
V, -Vs 



FIGURE 4. AC-Coupled +100V Difference Amp Using the 
INA106 Requires No Trims. 



SELECTION GUIDE 

(AC-coupled difference and instrumentation amplifiers) 
v s - ±15V 







COMMON MODE 


DIFFERENTIAL 


NOISE 


BANDWIDTH 


HIGH PASS 




GAIN 


INPUT RANGE 


OFFSET RANGE 


(RTI) 


HWB) 


MULTIPLIER 


MODEL 


[VIM] 


m 


m 


[nV/VHz] 


[Hz] 


(See Text) 


INA117 


1 


±200 


±200 


550 


200k 


19 


INA10&" 


1 


±100 


±100 


300 


400k 


10 


INA105 


1 


±20 


±10 


60 


1M 


1 


INA106 


10 


±11 


±1 


30 


500k 


1 


INA101 


(2) 


±7 m 


±10 


! (!) 


6M«> 


1 


INA102 














INA103 














INA110 














INA120 















NOTES (1 ) Reverse-connected, see figures 3,4, and 5. (2) Gain is adjustable from 1 to 1 000+. Noise and bandwidth depend on Gain setting. INA1 03 has the lowest 
noise: InV/VHz, Gain = 1000. INA103 has the highest bandwidth: 6MHz, Gain = 1. INA102 is low power (750uA max). INA110 has FET inputs (l B = 50pA max). 
INA101 has lowest drift (.25uv/°C max). INA120 is a lower IQ INA101 with internal resistors for Gains of 1, 10, 100, and 1000. (3) Yesl, the common-mode input 
range of standard IAs is only about ±7V with ±10V v^; see "Extended Common-Mode Instrument Amps", Electronic Design, December 22, 1988, pp 67, 68. 




The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR -BROWN 




APPLICATION BULLETIN 



,AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



+200V DIFFERENCE AMPLIFIER WITH 
COMMON-MODE VOLTAGE MONITOR 

By Art Gass and R. Mark Stitt (602) 746-7445 



55 



The INA117 is a monolithic difference amplifier with the 
unique ability to accept up to ±200V common-mode input 
signals while operating on standard ±15V power supplies. 
Using on-chip high-voltage resistor dividers, the INA117 
rejects common-mode signals up to ±200V and translates a 
0V to ±10V differential input signal to a 0V to +10V 
ground-referenced output signal. 

In some applications it is also necessary to monitor the 
common-mode level of the input signal. A common-mode 
level monitor can be implemented with the addition of an 
external op amp or two. Even though standard signal level 
op amps are used, the circuit remains protected for momen- 
tary common-mode or differential overloads up to ±500V. 

If precision is not required, the circuit shown in Figure 1 can 
be used to monitor the common-mode voltage with a maxi- 
mum error of about ±5V. This implementation actually 
monitors the common-mode level of the INA117 nonin- 
verting input (pin 3). The circuit works by measuring the 
current in reference pins 1 and 5, which are normally 
connected to ground. Amplifier A l forces the reference pins 
to a virtual ground through feedback resistors R 6 + R r The 
normal operation of the INA117 is unaffected since its 
reference pins are connected to virtual ground. Resistors R 3 



v 20 — 



380kQ 



"3 

380kn 



380kfl 

-vW~ 




21.1kQ 



20kQ 



INA117 



100pF 



Re " R 7 
5kQ 10WJ 




-O -V 3 /20 



FIGURE 1. INA117 with V 3 Common-Mode Voltage 
Monitor. 



and R 4 in the INA1 17 form a voltage divider so that the top 
of R 4 is at V/20. Feedback of the op amp in the INA1 17 
forces the voltage of its inverting input to be equal to its 
noninverting input so that the top of resistor R 5 is also at V 3 / 
20. The common mode level of V 3 is therefore related to the 
current flowing out of pins 1 and 5. 

I 1+5 = (V 3 /20)/(R 4 IIR 5 ) 
If 

R 6 + R 7 = R 4 II R 5 
then 

A, OUT = -V 3 /20. 

Where 

I 1 + 5 = total current flowing out of INA1 17 pins 1 and 5 [A] 
R 4 II R 5 = parallel combination of R 4 and R 5 [Q] 
R 4 II R 5 = (R 4 «R 5 )/(R 4 +R 5 ), nominally 10.27kQ 
A, 0UT = A, output voltage [V] 

The signal is scaled by 1/20 so the output of A, does not 
exceed its maximum of ±10V with common-mode inputs of 
±200V. If smaller maximum common-mode voltages are to 
be monitored, the value of R 6 + R 7 can be increased for more 



Although the resistor ratios in the INA117 are accurately 
laser trimmed, the absolute resistor values can vary by as 
much as ±25%. For better accuracy, the circuit must be 
calibrated. To calibrate the gain, short pins 2 and 3 of the 
INA117 to ground, offset adjust A ] for 0V at its output, 
connect pins 2 and 3 to a known V REF (such as +10V or 
+ 100V), and adjust R 7 for an A, output of -V REF /20. 

By definition, the true common-mode input voltage of the 
INA117 is (V 2 + V 3 )/2. The actual common-mode voltage 
can be monitored with the addition of a second op amp as 
shown in Figure 2. The second op amp is connected to sum 
the -V 3 /20 output of A, at a gain of -1 V/V with the V 3 - V 2 
output of the INA1 17 at a gain of -1/40V/V to produce an 
output of V CM /20. 



E 

3 



O 

'a. 



e l990 Burr-Brown Corporation 



AB-010A 





Primed in U.S.A. September. 1990 



Calibrate the Figure 2 circuit as before, adjusting R 7 for an 
A, output of V REF /20. Then, ground pin 3 of the INA117, 
connect pin 2 to +10V and trim R 9 for 0.025V at the output 
of A,. If resistors R 8 , R 9 , and R 10 accurately ratio match, 
adjustment of R 9 is unnecessary. 

Of course, if connection of additional components to the 
INA1 17 inputs is acceptable, the circuits shown in Figures 



3 and 4 can be used to monitor the common-mode input 
voltage. With these circuits, calibration is not required if 
accuracy commensurate with the tolerance of R 6 , R 7 , and R g 
is acceptable. As before, either R, or R g can be omitted to 
monitor the common-mode voltage of just one input. If R 7 or 
R g is omitted, double the value of R 6 . 



VaO--^- 



Ri 

380W2 



R 3 
380ki2 



n 2 
380ktt 



"5 

21.1kn 




INA117 



400kn 
WW - 



100pF 



R 6 " R 7 

5kn i0kn 




R 8 

10k£J 



100pF 




Vcm/20 



FIGURE 2. INA1 17 with True Common-Mode Voltage Monitor. 



v 2 o- 



'3 O- 



R, 

380kn 



n 3 

380kli 





INA117 



— O 

Vout=V 3 -V 2 



1MQ 



R 6 
24.9kfl 

-vW-n 




OPA177; 

+ ^ Vqut- -Vcm/20 



v 2 o- 



'3 O- 




R, 

380kn 



"3 

380kn 



21.1W1- 




INA117 



— O 

V ut=V 3 -V 2 



•1M£2 




Vout = +Vc„/20 



FIGURE 3. External CMV Monitor, Inverting. 



FIGURE 4. External CMV Monitor, Noninverting. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility tor inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR - BROWN 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



INPUT OVERLOAD PROTECTION FOR THE RCV420 
4-20MA CURRENT-LOOP RECEIVER 



By R. Mark Stitt and David Kunst (602) 746-7445 



Because of its immunity to noise, voltage drops, and line 
resistance, the 4-20mA current loop has become the standard 
for analog signal transmission in the process control indus- 
try. The RCV420 is the first one-chip solution for converting 
a 4-20mA signal into a precision 0-5V output. Although the 
on-chip current sensing resistor is designed to tolerate mod- 
erate overloads, it can be damaged by large overloads which 
can result from short circuits in the current loop. Complete 
input protection from short circuits to voltages of 50V or 
more can be afforded with the addition of the relatively 
simple circuitry shown in this bulletin. 

The complete protected 4— 20mA current loop receiver cir- 
cuit is shown in Figure 1 . The RCV420 is connected for a 0- 
5V output with a 4-20mA current sink input. For a 4-20mA 
current source input, connect the input to pin 3 instead of pin 
L An on-board precision +10.0V buried zener voltage refer- 
ence in the RCV420 is used to offset the span (for 0V out 
with 4mA in) via pin 12. It can also be used for powering 
external circuitry such as the voltage dividers used to set the 
underrange/overrange comparator thresholds. 



An LM193 dual voltage comparator is used to detect i 
range and overrange conditions at the output of tl 
The LM193 is designed to operate from a single power 
supply with an input common-mode range to ground. In this 
application the LM193 is operated from a single +15V power 
supply for input common-mode range compatibility with the 
RCV420 output. The open-collector LM193 comparator 
outputs are connected through lOkfl pull-up resistors to a 
+5V supply for compatibility with TTL and similar logic 
families. 

The RCV420 has a gain of 0.3125V/mA and a 4mA span 
offset (a 4mA-20mA input produces a 0V-5V output). 
Under input open circuit conditions (0mA input), the output 
of the RCV420 goes to -1.25 V. To level-shift the output up, 
for a minimum of 0V at the comparator inputs, it is summed 
iltage reference through the lOkO, 1.27k£2 
The table below shows selected operating 



with the 10.0V voi 
resistor network. The 



points for the RCV420 input/output and the comparator 
input. 



+15VI 



-15 V 



AT&T 
LH1191 
Solid-State 
Relay 



r 



3 0- 




92k£2 



^Wv- 

11.5kn 



4-20mA 
Input 



+5V 



10.0V 
Reference 



13 



12 



15 



10.0V 



10 



+15V 



1MQ- 



555 
Timer 



1uF 



© " — VW 



470Q 

Overrange 
Output 



. 10k£l <10kQ 



1 

1 ~J ~0.01uF 



47kn 

-vw- 



2N3904 




0-5V 



iokn 



10kfl S 10k£2 
6.95V 



T 




Output 



FIGURE 1. Input Protected RCV420. 

°1990 Burr-Brown Coiporation 



AB-014 



Printed in U.S.A. July, 1990 



SELECTED OPERATING POINTS 
FOR RCV420 AND COMPARATORS 



RCV420 INPUT 
(mA) 


RCV420 OUTPUT 
(V) 


COMPARATOR INPUT 

(V) 





-1.250 


+0.017 


2 


-0.625 


+0.572 


4 


0.000 


1.269 


20 


5.000 


5.563 


25 


6.563 


6.950 


36 


10.000 


10.000 


NOTE: (1) From the 10kQ, 1.27W2 summing network. 



The underrange comparator threshold is set at 0.57V by the 
lOkQ, 604Q. resistor divider connected to the 10.0V refer- 
ence. The comparator output goes high when the input to the 
current loop receiver goes below 2mA. The underrange 
output is TTL compatible. 

The overrange comparator threshold is set at 6.95V by the 
10kt2, 22.9kQ resistor divider connected to the 10.0V refer- 
ence. The output of the overrange comparator goes low when 
the input to the current loop receiver exceeds 25mA. 
With a 36mA current loop input, the overrange comparator 
input is 10V. For a 36mA overload set-point, the overrange 
resistor divider can be eliminated by connecting the overload 
comparator input directly to the 10.0V reference output of 
the RCV420. 

The overrange comparator is connected so its output will go 
low on overrange to trigger the ensuing active overload 
protection circuitry. If the overload protection circuitry is not 
used, the inputs to the comparator can be reversed so its 
output will go high on overload. 

The current sense resistors within the RCV420 are rated for 
overloads of up to 40mA continuous and for momentary 
overloads of up to 0.25A with 0.1s maximum duration and 
1% maximum duty cycle. Overloads within these limits will 
not damage or degrade the rated performance of the receiver. 
If the 75Q. sense resistor were shorted to 48V (a common 
current loop supply voltage), the overload current would be 
0.64A producing an I 2 • R power dissipation in the resistor of 
30.7W. With a package thermal resistance (0 JA ) of 70°C/W, 
this would result in a theoretical junction temperature rise in 
excess of 2000°C. The input resistor would fuse, destroying 
the device, before the package temperature actually reached 
2000°C. For input short circuits up to 3V, the current is 
limited to a safe 40mA by the 75£2 sense resistor within the 
RCV420. To prevent possible damage, external means are 
required to protect the RCV420 sense resistors from input 
short circuits to potentials greater than 3V. 

The least expensive input short circuit protection is a resistor 
connected in series with the current loop at the receiver input. 
Select the resistor so that the input current under short-circuit 
conditions will be limited to 40mA by the series combination 
of the protection resistor and the 75£2 current sense resistor 
internal to the RCV420. Short circuit protection to 48V 
requires a 1 1 25H resistor. 

Rp R oT E cT,oN=(V s /0.040)-75 (£2) 



The problem with using a series resistor for input overload 
protection is the added voltage drop in the input current loop. 
A 1125Q protection resistor in series with the 75£2 internal 
current sense resistor would result in a 24V drop at 20mA full 
scale input. In most applications the additional 24V burden 
can not be tolerated. 

Another input protection scheme which can be used when 
only a small series voltage drop can be tolerated is to use a 
0.032 A fast-acting fuse (such as Littlefuse 217000 series, 
type F) in series with the current loop. This fuse adds 
negligible voltage drop to the current loop, and blows in less 
than 0.1s with an overload of 128mA or more. The problem 
with a fuse is that it must be replaced when it blows, and the 
cost of maintenance can be very high. 

The active protection scheme shown in this application 
overcomes the disadvantages of resistor and fuse protection. 
It uses a solid-state relay for current loop interruption. After 
an interrupt time delay designed to provide a safe 1% 
maximum overload duty-cycle, the circuit resets automati- 
cally. The LH1 191 solid-state relay used has a maximum on 
resistance of 33Q which adds less than 0. IV of burden to the 
current loop at 20mA full scale input. Low receiver burden 
allows longer field wiring (with higher resistance) for remote 
sensors, and extra compliance for "intrinsically safe" barriers 
or other series connected receivers. 

The solid-state relay is ideal for the resetable protection task. 
It is inexpensive as compared to a mechanical relay (less than 
$1.00), and because it is solid-state, it will not "wear out" if 
cycled continuously. The LH1 191 is a single-pole, normally 
open switch rated for 280V, 100mA outputs. Relay overload 
currents are clamped to 210mA by current limiting circuitry 
internal to the relay. An extended clamp condition, which 
increases relay temperature, results in a reduction of the 
internal current limit to preserve the relay's integrity. 

Protection circuitry interrupt timing is provided by a 555 
timer connected as a monostable multivibrator (one shot). 
Under normal conditions, the output of the one shot is low 
holding the solid-state relay on by forcing approximately 
8mA through the LED as set by the series-connected 470Q 
resistor. When more than 25mA flows into the current loop 
receiver, the overload comparator triggers the one shot. With 
the values shown, the one shot output goes high, turning off 
the LED and the solid-state relay for about one second. At the 
end of one second the circuit automatically resets turning the 
relay back on. If an overload still exists, the cycle repeats. 
The overload current applied to the RCV420 is limited to 
about 210mA by the current limit of the solid-state relay and 
the 75Q sense resistor internal to the RCV420. The one 
second cycle time of the overload circuitry assures safe 1 % 
maximum overload current duty-cycle. The input to the 
circuit can be shorted to a 50V power supply continuously 
without damaging or degrading the accuracy of the RCV420. 
A short life-test was performed on a prototype circuit. After 
168 hours with the receiver input shorted to 50V, there was 
no detectable change in receiver accuracy within the 0.005% 
resolution of the test system. 



Since the overload protection circuitry interrupts the current 
loop, a logic gate is needed to prevent a false indication of 
open circuit. The 2N3904 transistor is wire-ORed to the 
underrange comparator output, assuring it will go high only 
during actual underload conditions. The l|iF capacitor con- 
nected to the 470£2 relay drive resistor delays relay turn-on 
to prevent possible logic race conditions which could pro- 
duce a false underrange output logic "sliver". The capacitor 
can be omitted if this is not a concern. 



BURR - BROWN 




APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



61 



EXTENDING THE COMMON-MODE RANGE 
OF DIFFERENCE AMPLIFIERS 

By R. Mark Stitt (602) 746-7445 



Extending the common-mode range of difference amplifiers 
allows their use in a wider variety of reduced power-supply 
applications. 

The INA1 17 has a specified common-mode input range of 
±200V when operating on standard ±1 5V power supplies. At 
power-supply voltages above ±13V, the INA1 17 input range 
is limited to ±200V by the power capabilities of its internal 
input resistors. On reduced power supplies, the input range 
is limited by the common mode input range of the internal 
op amp. 

The linear common-mode input range of the internal op amp 
extends to within 3V of its power supply voltage. For 
example, with a ±15V power supply, the common-mode 
input range of the internal op amp is ±12V. Because the 
INA1 17 internal resistor network divides the input by 20, the 
actual input range of the INA1 17 would be 20 • (+12V), or 
240V, for +15V power supplies. Similarly, reducing the 
power supply voltage to ±6V will limit the input common- 
mode voltage to ±60V. 

There are two approaches to boosting the common-mode 
input range for reduced power supply applications: Offset- 
ting the common-mode range by a fixed amount, and dy- 
namically adjusting the common-mode range to follow the 
input common-mode signal. 



OFFSETTING THE INPUT COMMON-MODE 
RANGE WITH A CONSTANT VOLTAGE 

In many applications, the common-mode signal range is 
known and the common-mode input range of the difference 
amplifier can be adjusted to coincide with the required 
range. For example, the ±60V common-mode range of the 
INA1 17 operating on +6V supplies could be shifted to range 
from +0V to +120V, or +50V to +170V. 

To offset the common-mode range, the reference connection 
of the difference amplifier is connected to an offsetting 
voltage, V , instead of ground. With the reference connected 
to an offsetting potential, a second difference amplifier must 
be used to refer the output back to ground. 

One way to offset the input voltage is to connect the 
reference pins 1 and 5 to the negative supply voltage as 
shown in Figure 1. Another possibility is to derive the offset 
voltage from a zener diode connected to the negative power 
supply as shown in Figure 2. In either case, the total 
common-mode range of the INA117 is unchanged and 
shifted by -19 • (V x ). 




v 2 o 



v 3 o- 



380kfl 



380kn 



R 5 . 
2i.ikn: 




20kil 



5 4 



-o v+ 



25kQ 



R 2 
25kU 



R 3 

25kn 




-o v = v 3 -v 2 

-3V> V o >-10V 

Swap A 2 pins 2 and 3 for: 

10V > V D > 3V 

also; 



«V + ) - 5V) > V D > <(V-) + 3V) 
O v- 



V„ =V- 



m 

T— 

E 

3 



a> 



CD 

c 
o 

(0 

o 

Q. 
CL 

< 



FIGURE 1. Offsetting the INA1 17 Common-Mode Input Range Using the Negative Power Supply as a Reference. 



e 1990 Burr-Brown Coiporation 



AB-015 



Printed in U.S.A. August, 1990 



v 2 o- 



v,o- 



380kfl 

WW- 



n 3 

380kfi 



2i.ikn: 



V x = (V-) + 3.3V 



-10k£2 



1N4684^ 

3.3V ' 



25kfi 



25k£2 



-o v+ 



R 2 
25kn 




1 



-o v = v 3 -v 2 

0V>V o >-10V 

Swap A 2 pins 2 and 3 for: 

10V > V > 0V 

also; 

<(V + ) - 5V) > V G > ((V-) + 3V) 
O V- 



FIGURE 2. Offsetting the INA1 17 Common-Mode Input Range with a Zener Reference. 



Since the input voltage can swing to within 3 V of the power 
supply, the following relationships apply for the INA1 17: 

V R = 20 • [(V+) + IV-I - 6V] 

V L = 20 • [(V-) + 3V] - 19 • V x 

V = V - V 

Y H V R V L 

Where 

V R = total common-mode range [V] 

V L = minimum common-mode signal [V] 

V H = maximum common-mode signal [V] 

V+, V- = positive, negative power supply [V] 

IV-I = absolute value of the negative power supply [V] 

V x = offset voltage (from ground) [V] 



POWER 
SUPPLY 


COMMON-MODE INPUT RANGE (V) 


V x =0". 




V x =(V-) + 3.3P> 


±15V 


-240 to +240' 4 ' 


45 to 525 w 


-18 to 462< 4 > 


±12V 


-180 to +180 


48 to 408< 4 > 


-15 to 345 ,4 > 


±9V 


-120 to +120 


51 to 291 ' 4 ' 


-12 to 228< 4 > 


±6V 


-60 to +60 


54 to 174 


-9 to 1 1 1 



NOTES: (1) Reference connected to GND (normal operation). (2) Refer- 
ence connected to V-fsee Figure 1). (3) Reference connected to V- 
through 3.3V zener (see Figure 2). (4) Voltages greater than ±200V are 
shown for reference only. INA117 maximum rated operating voltage is 
±200V. 



TABLE I. INA117 Common-Mode Input Range for Se- 
lected Power Supplies and Reference Offsets. 

The same principles can be applied to the INA105 difference 
amplifier as shown in Figures 3 and 4. With an allowable 
voltage swing to within 3V of the power supply, the following 
relationships apply for the INA105: 

V R = 2 • [(V+) + IV-I - 6V] 

V L = 2 • [(V-) + 3V] - V x 



ADJUSTING THE COMMON 
MODE RANGE DYNAMICALLY 

Another way to boost the common-mode range of a differ- 
ence amplifier is to drive the reference connection dy- 
namically in response to changes in the input. A circuit to 
boost the input range of the INA1 17 is shown in Figure 5. 
A third amplifier, A 3 , along with resistors R 7 , R 8 , and R 6 is 
used to derive, invert, and scale the input level presented to 
the reference connection. 

The value for R 6 depends on the power supply voltages and 
op amp used for A 3 . To maximize the common-mode range, 
R 6 should be selected so the output of A 3 is at its maximum 
swing limit when the inputs to the difference amplifier op 
amp are at 3V from the opposite power supply. The OPA1013 
is a good choice for A 3 since its outputs are guaranteed to 
swing within 2V of the power supply rails. 

Using the OPA1013 op amp for Aj, and considering the 
allowed swing to within 3V of the power supply voltage, the 
following relationships apply for the INA117. 

V CM =±{20.((V+)-3V)-19- V x ] 

V x = (V-) + 2V 

R 6 = -0.5MQ.V X /V CM 

Where: 

V CM = common-mode input range [V] 
R 6 = value of R 6 [Q] 



POWER 
SUPPLY (V) 


(V) 


R 6 
(kn) 


±15 


±4871" 


13.3 


±12 


±370'" 


13.7 


±9 


±253"' 


13.7 


±6 


±136 


14.7 


NOTES: (1) Voltages above ±200V are shown for reference only. INA1 17 
maximum rated operating voltage is ±200V. 



TABLE II. INA117 Common-Mode Input Range for Se- 
lected Power Supplies Using Figure 5 Circuit. 



v 3 o 




o v = v 3 -v 2 

-3V> V o >-10V 
Swap A 2 pins 2 and 3 for: 
10V > V D >3V 

also; 

«V + )-5V)>V >((V-) + 3V) 
O V- 



v v = v- 



FIGURE 3. Offsetting the INA105 Common-Mode Input Range Using the Negative Power Supply as a Reference. 



v 2 o- 



25kfl 



R 3 

25kQ 




4 INA105 



25kfl 



•10k£2 
3 



-O V+ 



25k£l 



25kQ 



25kfi 




4 IN A 105 



y 1N4684 

3.3V 



-o v = v 3 -v 2 

0V> V o >-10V 

Swap A 2 pins 2 and 3 for: 

10V>V o >0V 

| 

Ialso; 
((V + )-5V)>V >((V-) + 3V) 



-O V- 



V x = (V-) + 3.3V 



FIGURE 4. Offsetting the INA105 Common-Mode Input Range with a Zener Reference. 



v 2 o 



v 3 o 







380k£2 



R 3 

380kQ 

-vW- 



2i.ikn : 



R 7 

1MQ 

iMn 





A 3 



6 2 



25kQ 25k£l 



25kn 

vw- 



— I— 




-o v = v 3 -v 2 



1 



FIGURE 5. Boosting the INA1 17 Common-Mode Input Range Dynamically. 



at just one input pin (either pin 2 or 3). In this case one 
common-mode sense resistor (either ^ or R 8 ) can be omit- 
ted. The value of the feedback resistor, R 6 , must then be 
doubled. 

The same principles can be applied to the INA105 difference 
amplifier as shown in Figure 6. Using the same 3V, 2V rules, 
the following relationships apply for the INA105. 

V CM = ±{2.((V+)-3V)-V x } 

V x = (V-) + 2V 

R 6 = -0.5MQ.V X /V CM 



OUTPUT RANGE LIMITATIONS 

Keep in mind that with any of these techniques, the 
common-mode range refers to the input of the difference 
amp only. To make use of the extended common-mode 
range, the output swing limitations of the difference amp 
must also be observed. 

The output of the INA1 17 or INA105 is guaranteed to swing 
at least +10V on +15V power supplies. However, a negative 
output can actually swing to within 3V of the negative power 
supply (to -12V on +15V supplies). 

With zero differential input voltage to the difference amplifier, 
the output will be at zero volts with respect to the reference 
connection, V x . The circuits in Figure 1 or 3 will not work 
with zero differential input. Since the difference amp reference 
pin is connected to V-, the output of the difference amp 
would saturate to its negative swing limit in an attempt to 
swing to V-. For the circuit to work, the differential input 
must be at least 3V so that the output of the difference 
amplifier is at 3V from V-. The input to the difference 
amplifier can be either +3V or -3V and the input connec- 
tions (pins 2 and 3) can be interchanged to provide the 
proper output swing. 

The circuits in Figures 2 and 4 will function with zero 
differential input since the reference is connected 3.3V from 
V-. Output swing in response to input signal must, however, 
always be in the positive direction. As before, the inputs of 
both difference amplifiers can be connected to accommodate 
any polarity of input/output swing. 



circuit, the V x terms in the equations must be replaced by: 
[(V-) + 3V + V sw ] for negative swings 
and by 

[(V+) - 5V - V sw ] for positive swings 
Where: 

V sw = difference amp output swing relative to reference, 

(V sw = difference amp differential input since the gain =1) 

The boosted common-mode range for positive inputs is 
different than for negative inputs due to the differences in 
the difference amplifier output swing limitations: 

For positive common-mode inputs: 

V CM „ = 20.((V + )-3V)-19.V XH 

R 6H = -0.5Mfi.V XH /V CMH 

V XH =[(V-) + 3V + V sw ] 
For negative common-mode inputs: 

R 6L = -0.5M£2.V XL /V CMH 
V xl=[( v+ )-5V-V sw ] 
Where: 

V CMH = highest common-mode input voltage [V] 

V CML = lowest common-mode input voltage [V] 

Since only one value for R6 can be used, the smaller value 
must be selected if the common-mode input is bipolar. The 
total common-mode swing is limited by this value. 

Reducing the difference amplifier output swing increases the 
possible common-mode input range. If a higher output 
swing is needed, add gain after the difference amplifier as 
shown in Figure 7. In this circuit an optional f ^ = 1kHz 
filter is added ahead of the gain stage. The filter reduces 
output noise at the expense of signal bandwidth reduction. If 
filtering is not desired, connect the difference amp output 
directly to the noninverting input of the output amplifier. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



v 5 o- 



v 3 o- 



25k£i 



25kfi 



R 3 
Ski 



^3 

25kfl 




+ / A, 

R 4 INA105 

25k£J 

vw 



R7 



1 3 




R1 

25k£l 



R3 

25k£i 



25kQ 




-o v = v 3 -v 2 



R 4 INA105 

25ki2 





1 



FIGURE 6. Boosting the INA105 Common-Mode Input Range Dynamically. 




FIGURE 7. Boosted Common-Mode Input Range INA117 with Noise Filtering and Added Gain after the 2nd Difference 
Amplifier to Further Extend INA1 17 Common-Mode Input Range. 



BURR - BROWN 




APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



67 



BOOST AMPLIFIER OUTPUT SWING 
WITH SIMPLE MODIFICATION 

By R. Mark Stitt and Rod Burt (602) 746-7445 



In many applications it is desirable for the output of an 
amplifier to swing close to its power supply rails. Most 
amplifiers only guarantee an output swing of ±10V to ±12V 
when operating on standard ±15V power supplies. With the 
addition of four resistors and a pair of garden-variety tran- 
sistors, the INA105 or INA106 difference amplifiers can be 
modified to provide nearly a full +15V output swing on 
+15V supplies. 

Figure 1 shows the modified circuit for the INA105. The 
combined INA105 quiescent current and output current 
flowing from its power-supply pins drives external transis- 
tors Q, and Q 2 through base-emitter connected resistors R 3 
and R 4 . Q, and Q 2 are arranged as common-emitter ampli- 
fiers in a gain of approximately 1.7V/V (1 + 750Q/lkI2) so 
that the INA105's output only needs to swing about ±9V for 
a ±15V swing at the buffer output. Figure 4 shows the 
boosted INA105 driving a lk£2 load to within a fraction of 
a volt of its ±15V power supplies. Figure 4 is a multiple 
exposure scope photo showing the composite amplifier 
output and the power-supply voltages. 



+15VO 




■In o- 



In O- 



INA105 



200Q 



Q1 

2N3906 



R 2 




R 4 




-15V O- 




NOTES: (1 ) R 2 = 750Q for INA1 05. R 2 - 1 kQ for INA1 06 on ±12V to ±1 8V 
power supplies. R 2 = 2kn for INA106 on +8V to ±18V p 



FIGURE 1 . External Transistors Q, and Q 2 Add Output Boost 
so the Difference Amplifier Can Drive Loads 
Close to Its Power-Supply Rails. 



Even though there is gain in the feedback of the INA105, the 
circuit is stable as shown by the small-signal response of the 
amplifier as seen in the scope photo, Figure 5. Since a unity- 
gain difference amplifier operates in a noise gain of two, 
gain can be added in its feedback loop without causing 
instability with the following restrictions: 1) the added gain 
is less than 2V/V, 2) the op amp in the difference amplifier 
is unity gain stable, and 3) the phase shift added by the gain 
buffer is low at the unity gain frequency of the op amp. All 
stability requirements are met when using the INA105. 

To understand the details of the composite amplifier, con- 
sider the block diagram, Figure 2. Resistors R, and R 2 set the 
gain of the buffer amplifier A 2 . The buffer amplifier is a 
current-feedback op amp formed from the output transistors 
in the INA105 and the external transistors, Q, and Q 2 . The 
current feedback amplifier gives wide bandwidth and low 
phase shift. Figure 3 shows one of two complementary 
current-feedback amplifiers formed from the NPN output 
transistor in the INA105 and the external PNP transistor, Q,. 
This current-feedback amplifier section is active for positive 
swings of the composite amplifier output. A complementary 
current-feedback amplifier, using external transistor Q 2 , is 
active for negative output swings of the composite amp. 




FIGURE 2. Block Diagram Showing Boost Circuit Feedback 
Arrangement. 

Because the maximum gain in the feedback of an INA105 is 
limited to 2V/V, the boosted circuit works best with power 
supplies of +12V or more. The INA105 doesn't have enough 
output swing on lower supplies to drive a gain-of-2 buffer to 
the power supply rails. For boosted output swing on lower 
supplies, consider the INA106 gain-of-10 difference ampli- 
fier. Although the op amp in the INA106 is not unity gain 
stable, the INA106 is stable with added gain in its feedback 
of up to 3 V/V. This allows full output boost on lower voltage 
supplies. Scope photograph Figure 6 shows the boosted 



n 

E 
3 



"5 
m 



CO 

o 

a 
< 



e 1990 Burr-Brown Corporation 



AB-016 



Printed in U.S.A. September, 1990 



snowing tne composite amplifier output and the power- 
supply voltages. Scope photograph Figure 7, shows the 
small signal response of the INA106 with a gain-of-3 feedback 
buffer. 

A word of caution: To obtain the boosted output swing, 
output protection circuitry was eliminated. There is no 
current limit in the output buffer. A short circuit at the output 
may destroy the external output transistors. Still, this simple 
modification is an effective means to obtain wide output 
swing. 

So long as the stated stability requirements are observed, this 
technique can be applied to other op amp circuits. 



v+ o 




-In o- 
CFB Amp 



+ln ^ 
CFB Amp 



INA105 

Circuit 
Fragment 



A 
ToQ 2 
Collector 



-o v n 



NOTES: (1 ) Q, is the external 2N3906 PNP 
transistor. (2) Q 3 is the INA105 output NPN 



FIGURE 3. Circuit Detail Showing One-Half of the Sym- 
metrical Current-Feedback Amplifier Output 
Stage, A 2 in Figure 2. 




FIGURE 5. Small-Signal Response of Composite Amplifier 
Using INA105 and Buffer Amplifier with 750Q, 
lkQ Feedback Resistors. 




FIGURE 6. Triple Exposure Showing ±8V Power Supplies 
and Composite Amplifier Output Driving lkQ 
Load. 





FIGURE 7. Small-Signal Response of Composite Amplifier 
Using INA106 and Buffer Amplifier with 3k£2, 
lk£2 Feedback Resistors. 



FIGURE 4. Triple Exposure Showing ±15V Power Supplies 
and Composite Amplifier Output Driving lkQ 
Load. 

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN E 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR- BROWN 




"APPLICATION BULLETIN 



Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 

TO 20mA RECEIVER USING RCV420 

By David Kunst and R. Mark Stitt (602) 746-7445 



69 



Many industrial current-loop applications call for conver- 
sion of a to 20mA input current into to 5V output. The 
RCV420 is intended primarily as a complete solution for 
precise 4 to 20mA to to 5V conversion. But, with the 
addition of one or two external 1% resistors, the RCV420 
can also accurately convert a to 20mA input into a to 
5V output. 

The recommended hook-up for 0-20mA/0-5V conversion 
is shown in Figure 1. To reduce the gain from 5V/16mA 
to 5V/20mA, the internal 75t2 sense resistor is paralleled 
with a 301 Q, 1% external resistor connected between pins 
1 and 2. 

Even though the external paralleling resistor has a 1% 
tolerance, the worst-case gain error of the current-to- 
voltage conversion will be only 0.5%. This is because the 
parallel combination of an external 30112 resistor and the 
internal 75Q resistor is dominated by the internal resistor. 

A tighter tolerance on the external paralleling resistor 
would not significantly improve the gain accuracy. This is 
because the internal 75Q sense resistor also has a toler- 



ance of 1%. The high gain accuracy of the RCV420 
transfer function comes from a fine laser trim of the 
internal amplifier's gain which compensates for any error 
in the 75£2 internal sense resistor. So even if the sense 
resistor were replaced by a resistor of exact value, the gain 
error could be as much as 1%. 

For best common-mode rejection performance, a second 
30 1Q external resistor should be connected between pins 
2 and 3 in parallel with the other internal 75Q sense 
resistor. Without it, 86dB CMR would be degraded to 
about 80dB. If high CMR is not needed, the second 
resistor shown can be omitted. 

To eliminate the offset, used for 4-20mA/0-5V conver- 
sion, the "Ref In" (pin 12) must be connected to ground 
instead of to the 10V reference. The "Ref Out" and "Ref 
Feedback" (pins 10 and 11) should still be connected 
together to prevent the reference circuitry from locking- 
up. Even though the 10.0V reference is not used for span 
offsetting, it is a precision reference which may be useful 
for other circuitry. 



+15VO O- 



15V 



301 n- 




0-20mA l 
Input | 



301 a 



RCV420 




-75Q 



300kn 




92kn 

n.5kn 



i.oikn- 



iookn 



10.0V 
Ref 



13 



12 



15 



14 



-ov 

0-5V 



10 



-O10.0V OUT 



11 



00 



.a 
E 

3 



FIGURE 1. 0-20mA/0-5V Receiver Using RCV420. 



I 
3 
CO 

c 
o 

I 

a. 
a. 
< 



®1990 Burr-Brown Corporation 



AB-018A 



Printed in U.S.A. February, 1991 



294£T 



0-20mA I 
Input ! I 



294Q" 



+15VO 
M6 



1 



15V 



RCV420 



300kn 
■ 75a 



-75n 




-W\A- 

92k£2 

-MA- 

11.5k£l 



i.oikn: 



300kI2 



100kI2 



10.0V 
Ref 



13 



12 



' 200O 



14 f I 0-5 



V 
5V 



10. 



11 



-O10.0V OUT 



FIGURE 2. Gain Trimmable 0-20mA/0-5V Receiver Using RCV420. 



If better gain accuracy is required, use the gain trim circuit 
shown in Figure 2. This circuit uses a slightly lower value 
external resistor in parallel with the internal 75Q sense 
resistor and a potentiomenter in the feedback for fine trim 
of gain. Because of its small value, and the action of the 
"T" network feedback arrangement, the effect of the gain 
adjust pot on CMR is negligible. 

Of course, any mix of input/output polarity can be ob- 
tained by connecting the current source input to either pin 
1 or 3. 



INPUT CURRENT 


OUTPUT VOLTAGE 


INPUT CONNECTION 


to 20mA 


0to5V 


Pin 1 


to -20mA 


0to-5V 


Pin 1 


to 20mA 


0tO-5V 


Pin 3 


to -20mA 


0to5V 


Pin 3 



Gain-reduction paralleling-resistors for selected gains are 
shown in the table below. 



INPUT RANGE 


OUTPUT RANGE 


PARALLELING-RESISTOR 


to 20mA 
to 50mA 


to 5V 
0to5V 


301 £2 
35.7fl 



In general, to determine the value of the external parallel- 
ing resistor: 

R EXT = 



75Q 



I 



IN 



-1 



16mA 
Where: 

R EXT = External paralleling resistor (£2) 
1^. = Input current range (mA) 



BURR -BROWN 




APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 

BOOST INSTRUMENT AMP CMR 

DRIVEN SUPPLIES 

By R. Mark Stitt (602) 746-7445 



Ever-increasing demands are being placed on instrumenta- 
tion amplifier (IA) performance. When standard IAs can not 
deliver the required performance, consider this enhanced 
version. Dramatic performance improvements can be 
achieved by operating the input amplifiers of a classical 
three-op-amp IA from common-mode driven sub-regulated 
power supplies. 

Instrumentation amplifiers are designed to amplify low- 
level differential signals while rejecting unwanted common- 
mode signals. One of the most important specifications is 
common-mode rejection (CMR) — the ability to reject com- 
mon mode signals. AC CMR is especially important since 
the common-mode signals are inevitably dynamic — com- 
monly ranging from 60Hz power-line interference to 
switching-power-supply noise at tens to hundreds of kHz. 
With common-mode driven sub-regulated supplies, both the 
AC and DC CMR of the IA can be dramatically improved. 
Improved AC and DC power supply noise rejection is an 
added bonus. 

At the high gains often required, input offset voltage drift 
can also be a critical specification. In some applications, the 
low input offset voltage drift of chopper stabilized op amps 
might provide the best solution. But, since many of these 
chopper stabilized op amps are built using low voltage 
CMOS processes, they can not be operated on standard 
+15V power supplies. Operating the chopper stabilized op 
amps from common-mode-driven, sub-regulated +5V sup- 
plies allows them to be used without restriction in ±15V 
systems. 

THE THREE OP AMP IA 

To understand how the technique works, first consider the 
operation of the three op amp IA shown in Figure IA. The 
design consists of an input gain stage driving a difference 
amplifier. 

The difference amplifier consists of op amp A 3 and ratio 
matched resistors R t through R 4 . If the resistor ratios R/R, 
exactly match R 4 /R 3 the difference amplifier will amplify 
differential signals by a gain of R 2 /R, while rejecting com- 
mon-mode signals. The CMR of the difference amplifier 
will almost certainly be limited by resistor mismatch when 
a high-performance op amp is used for A 3 . A unity-gain 
difference amplifier requires a difficult 0.01 % resistor match 
for CMR of 86dB. 

Since the slightest input source impedance mismatch would 
degrade the resistor matching of the difference amplifier, a 
differential input, differential output gain-stage (A p A 2 , R FB1 , 



R FB2 , and R G ) is used ahead of the difference amplifier. The 
low output-impedance of the of the gain stage preserves 
difference amplifier resistor matching and maintains the 
CMR of the difference amplifier. The input amplifiers also 
provide high input impedance and additional gain. 

When designing a high CMR instrumentation amplifier, it is 
important to use a differential input, differential output 
amplifier using a single gain-set resistor (see Figure IA). In 
the Figure IA circuit, CMR is independent of resistor 
matching. Resistor mismatches degrade CMR in the two 
gain-set-resistor differential in/out amplifier (see Figure IB). 

To understand why CMR is independent of resistor match- 
ing in the single gain-set resistor amplifier, consider the 
Figure IA circuit. With a common-mode input signal, and 
no differential input signal, the voltage between V N and V p 
does not change. Therefore the voltage across R remains 
constant and, since no current flows in the op amp inputs, 
there is no current change in R rai or R ra2 , and the differential 
output voltage, V,-V 2 , does not change. Ideally then, with a 
perfect difference i 
and the CMRR is 




V p o 



Mismatches in gain-set resistors R FB1 and R re2 do not degrade IA CMR. 
GAIN = (1 + [R re , * R FB2 ]/R G ) (R^R,) 

" ^FBI = ^FB2 = ^FB' 

GAIN = (1 + [2.R FB ]/R G ) (R/R,) 



FIGURE IA. The Three Op-Amp] 



1991 Burr-Brown Corporation 



AB-025 



Printed in U.S.A. January, 1991 




NOTE: Mismatches between gain-set resistor pairs, R FB1 /R G1 and 
R FB2 /R G2 do degrade IA CMR. 



FIGURE IB. The Wrong Way to Make a Three Op- Amp 
Instrumentation Amplifier. 

In the Figure IB circuit, CMR does depend on resistor 
matching. Common-mode signals will cause different com- 
mon-mode currents to flow through R G1 and R G2 if their values 
are not matched. Then, if the ratio of R FB1 /R G1 is not exactly 
equal to the ratio of R FB2 /R G2 , there will be common-mode 
gain and the CMRR of the instrumentation amplifier will be 
degraded. 

Mathematically, for the two circuits: 

G DIFF = (V,-V 2 )/(V N -V p ) 
G cm = ( V ,-V 2 )/V cm 

For the single gain-set resistor circuit, Figure 1A: 

G DIFF = ( R FBI + ^2 + R G^G 

If R FB1 = R FB , = R ra , this becomes the familiar 

G D|FF = 1 + (2 • R FB /R G ) 
G CM = 

For the two gain-set resistor circuit, Figure IB: 



v N -v P 



G CM - (RFBl^Gl) ~ ( R FB2/ R G2) 

(The CMRR of the Figure IB circuit does depend on buffer 
amplifier resistor matching.) 

Where: 

G DIFF = Differential gain of the IA (V/V) 
G CM = Common-mode gain of the IA (V/V) 

See Figures IA and IB for V s and R s . 

Common-mode rejection ratio is the ratio of differential gain 
to common-mode gain. Adding gain ahead of the difference 
amplifier increases the CMR of the IA so long as the op 
amps in the gain stage have better CMR than the difference 



CMR (e.g. 80dB) at gain = 1 and a much higher CMR at 
higher gains (e.g. lOOdB at gain = 1000). 

Most high-performance op amps have better CMR than is 
available from difference amplifiers. Be careful when select- 
ing an input op amp though; the venerable "741 " op amp has 
a minimum high-grade CMR of 80dB, and the world's most 
popular op amp (1) , the LM324, has a min high-grade CMR of 
only 70dB. High performance bipolar input op amps have 
the best CMR. The OPA177 has a min CMR of 130dB. FET 
input op amps usually don't offer quite as much perfor- 
mance. The Burr-Brown OPA627 comes the closest with a 
min CMR of 106dB. 

LIMITING FACTORS IN IA PERFORMANCE 

The DC CMR of a standard IA can be improved by driving 
the power supply connections of the input op amps from 
sub-regulated power supplies referenced to the IA common- 
mode input voltage. Op amp CMR is limited by device 
mismatch and thermal feedback that occurs as the op amp 
inputs change relative to its power supplies. If the power 
supply rails are varied to track the common mode input 
signal, there is no variation of the inputs relative to the 
power-supply rails, errors which degrade CMR are largely 
eliminated, and CMR can be substantially improved. 

The AC CMR of the IA is limited by the AC response of the 
input amplifiers. The outputs of the input amplifiers in the 
IA follow the common mode input signal. As the frequency 
of the common-mode signal increases, the loop gain of the 
input op amps diminishes, and CMR falls off. 

For large common-mode signals, the slew rate of the input 
op amps can limit the ability of the IA to function altogether. 
This will happen when the maximum rate of change of the 
common-mode signal exceeds the slew rate limit of the op 
amp. For a sine wave, the maximum rate of change occurs 
at the zero crossing and can be derived as follows: 

V = V p • sin(2 • jc • f • t) 
dV/dt = 2 • 7C • f • V p • cos(2 • jc • f • t) 

At t = 0, 



dV/dt = 2 • jc • f • V p 
Slew rate limit = 2 • jc • f „ 



fi _ v n * (1 + (Rfb./Rqi)) - V P • (1 + (R FB 2/R G 2)) Where: 

DIFF _ ~ 



V = common-mode voltage vs time (t) 
V p = peak common-mode voltage 
Slew rate limit = maximum dV/dt 

f MAX = maximum common-mode frequency at amplitude V p 
beyond which standard IA fails to function due to 
slew-rate limit of input op amp. 

As with DC CMR, AC CMR can be improved by driving the 
power supply connections of the input op amps from com- 
mon-mode referenced sub-regulated supplies. Since neither 
the inputs nor the output of the amplifier change relative to 



( 1 ) According to its designer: Frederiksen, Thomas M., Intuitive IC Op Amps, 
National Semiconductor's Technology Series, 1984, back cover. 



73 



the power supply rails, nothing within the amplifier moves 
in response to the common-mode signal. No current flows in 
the phase compensation capacitors and the phase compensa- 
tion is therefore defeated for common-mode response. 

THE BOOSTED IA 

The complete circuit for the enhanced IA is shown in Figure 
2. In addition to the three op amp IA, it contains a buffered 
common-mode voltage generator, and +5V subregulated 
power : 



v N o- 



V p O 




Gain-of-10 
Difference Amplifier 
~~INA106 1 

R, R. 



100k£J 



-ov n 




100uA 
V4REF200 

C, 0.01 pF 



2kO- 





to +V S of 
A, & A 2 



C 2 0.01 uF 



100uA 
Vi REF200 



O 
-15V 



NOTE: Driving the power supplies of the input amplifiers of a three op 
amp IA from common-mode driven supplies can dramatically improve 
both AC and DC CMR. 



FIGURE 2. Boosted Instrumentation Amplifier. 



An INA106 gain-of-10 difference amplifier is used for the 
difference amplifier. The INA106 contains a precision op 
amp and ratio matched resistors R, through R 4 pretrimmed 
for lOOdB min CMR. No critical resistor matching by the 
user is required to build a precision IA using this approach. 

The common-mode signal driving the subregulated supplies 
is derived from resistor divider network, R 5 , R 6 . The network 
is driven from the IA inputs through unity-gain connected op 
amps A 4 and A 5 . These buffer amplifiers persevere the IA's 
high input impedance. In some applications the impedance 
of the R 5 , R 6 network connected directly to the IA inputs is 
acceptable and buffer amplifiers A 4 and A 5 can be deleted as 
shown in Figure 3. The signal at the R 5 , R 6 connection of the 
resistor divider is the average or common-mode voltage of 
the two IA inputs. 

The negative subregulator consists of A 6 , R 7 , C,, and a lOOuA 
current source (1/2 of Burr-Brown REF200). Since no cur- 
rent flows in the op amp input, lOOuA flows through the 
50k£2 resistor, R, forcing a -5V drop from the op amp input 
to its output. The op amp forces the negative input to be at 
the same potential as its positive input. The result is a a -5V 
floating voltage reference relative to the op amp noninverting 
input terminal. 

The positive subregulator is the same as the negative 
subregulation except for the polarity of the current source 
connection. 

The outputs of the positive and negative subregulators are 
connected to the power supplies of the input op amps A! and 
A 2 only. All other op amps are connected to ±15V power 
supplies. 

COMMON MODE RANGE OF BOOSTED IA 

The common-mode input range of the boosted IA is limited 
by the subregulated supply voltage. The outputs of the 
subregulator amplifiers, A 6 and A, must swing the common- 
mode voltage plus the subregulator voltage. The smaller the 
subregulator voltage, the better the common-mode input 
range. A subregulator voltage of ±5V was chosen because it 
is low enough to give good input common-mode range while 
it is high enough to allow full performance from almost any 
op amp. 

COMMON MODE RANGE OF BOOSTED IA 
IS AS GOOD AS STANDARD IA 

The common-mode input range of the boosted instrumenta- 
tion amplifier is as good as that of most integrated circuit 
IAs. It might seem that the subregulated supplies would 
reduce the IA's common-mode range. But because the 
boosted IA uses a gain-of-10 difference amplifier rather than 
a unity gain difference amplifier its common mode range is 
not limited by the input amplifiers. The common-mode input 
range of both the boosted IA and the standard IA is about 
±7V. 

That's right. With a 10V output, the common mode input 
range of a standard I A is only about ±7V, not +10V as many 
have been incorrectly led to believe. 



v N o- 



r 5 : 

iokn- 




-W\A 



Gain-of-10 
Difference Amplifier 

INA106 

R, R 2 

■WV— t (/W- 



R 6 - 
iokn- 



V P ID- 




NOTE: If high input impedance is not needed, 
the common-mode buffers (A 4 and A 5 from 
Figure 2) can be eliminated. 







50k£l 



C 2 0.01 pF 

100pA 
Vi REF200 



-15V 



FIGURE 3. Simplified Boosted Instrumentation Amplifier. 

The common-mode swing of a standard IA is limited by the 
output swing of the input amplifiers. The common mode 
range of the boosted IA is limited by the output swing of the 
subregulator amplifiers. 

Standard IAs use unity gain difference amplifiers for prac- 
tical reasons. Since standard IAs are designed for general 
applications, they must be adjustable to unity gain. Because 
it would be difficult for the user to maintain the resistor ratio 
matching necessary for good difference amplifier CMR, a 
fixed unity gain difference amplifier is provided. Gain ad- 
justment is made with the input amplifiers, where i 



is not critical for good CMR. Also, The more gain placed 
ahead of the difference amplifier, the better the IA CMR. 

To compare the limits on input common-mode range, as- 
sume the op amps used can all swing to within 3V of their 
power supply rails (i.e. they can swing to ±12V when 
operating on ±15V power supplies). 

In a standard IA, using a unity gain difference amplifier, the 
input amplifiers must provide a differential 10V output for 
a 10V IA output. With the input amplifiers in equal gains, 
each must deliver one half of the 10V differential signal. 



75 



v P o 




NOTE: You can make a high-voltage IA with the 
boosted IA by using high-voltage op amps for A 3 , A 6 , 
and A 7 while using high performance, signal level op 
amps such as the OPA177 for A, and A 2 . 



REF200 



R 8 

-w- 

50k£J 



1 V CM +5V 
to +V S of 
A, & A 2 



C 2 0.01 uF 



©I 



I 

< I 



-40V 



4. High Voltage Instrumentation 



With a common-mode input of 7V one input amplifier must 
deliver 7V common-mode plus 5 V differential — its 12V 
swing limit. 

The boosted IA also has a ±7V common-mode input limit. 
The subregulators are set at ±5V from the input common- 
mode signal. With a 7V common mode input, one of the 
subregulator outputs is at its 12V swing limit. 



In the boosted IA, using a gain-fo-10 difference amplifier, 
the buffer amplifiers must provide a differential output of 
only IV for a 10V IA output. With the input amplifiers in 
equal gains, each must deliver one half of the IV differential 
signal. With a common-mode input of 7V, one input ampli- 
fier must deliver 7V common-mode plus 0.5V differential 
for a total of 7.5V at its output which is no problem since the 
V is 12V (5V subregulated + 7V common-mode). 




1k 10k 
Frequency (Hz) 

NOTE: Both the standard and boosted IA use OPA177S for input 
amplifiers. The overall gain of the IA is 1 000V/V (input section gain = 1 00, 
difference gain = 10). The boosted IA gives more than 100/1 OMR 
improvement. Noise limits the DC CMR to slightly greater than 140dB 
referred to a +9dBm common-mode input signal. 



FIGURE 5. CMR vs Frequency Comparison between Stan- 
dard Three Op Amp IA and Boosted IA. 

SUBREGULATION IMPROVES PRECISION 

Lower power dissipation in the input op amps due to reduced 
power supplies can improve performance by reducing ther- 
mally induced low-frequency noise. In all semiconductor 
packages thermocouples are formed at various conductor 
interfaces. Matched-seal metal, side-braze ceramic, cerdip, 
and many plastic packages use Kovar leads. Significant 
thermocouples are formed between the lead plating and the 
Kovar. Thermocouples are also formed between the leads 
and the solder connections to the printed circuit. 

If thermal gradients are properly matched (at the amplifier 
inputs) the thermocouple errors will cancel. In practice, 
mismatches occur. Even under laboratory conditions, the 
error produced can be several tenths of microvolts — well 
above the levels achievable with low-noise amplifiers. At 
the output of a high-gain amplifier, the error will appear as 
low frequency noise or short-term input offset error. 

In signal op amp packages, much of the heat is conducted 
away through the leads. The resultant thermal gradient 
between the package and the printed circuit can be a major 
source of error. Air currents cool one lead more than an- 
other, resulting in mismatched thermal gradients. Operating 
the op amp on ±5V supplies (reduced from +15V supplies) 
decreases quiescent power dissipation and associated tem- 
perature rise by three-to-one, providing a commensurate 
reduction in thermally induced errors. 

PERFORMANCE OF 
BOOSTED IA vs STANDARD IA 

A performance comparison between the standard IA and the 
boosted IA in Figure 2 is shown in Figure 5. Amplifiers used 
for A, and A 2 are OPA177; A 3 is an INA106 gain-of-10 
difference amplifier; and A 4 to A 7 are an OPA404 quad op 




Input signal is ±2.5V, 2kHz. Output shows approximately 56dB CMR. 



FIGURE 5B. Common-Mode Input and Output of Standard 
Gain = 1000V/V IA Using LTC1050 Chopper 
Stabilized Op Amp. 




Input signal is ±2.5V, 2kHz. Output shows improvement over standard 
IA to approximately 82dB CMR. 



FIGURE 5C. Common-Mode Input and Output of Boosted 
Gain = 1000V/V IA Using LTC1050 Chopper 
Stabilized Op Amp. 

amp in the boosted circuit. Overall gain of the IA is set at 
1000V/V. The OPA177 is an improved version of the 
industry standard OP 07. It offers 10|aV max V os and 0. l(iV/ 
°C max V 0S /dT. The OPA404 is used for speed and bias 
current. The FET inputs of the OPA404 do not add loading 
at the input of the IA. The speed is high as compared to the 
OPA177 giving a good improvement of CMR vs Frequency. 
The CMR plots were made using an HP4194A gain-phase 
analyzer with an input signal to the IA of +9dBm. As you 
can see, CMR vs Frequency is boosted dramatically. At 
2kHz, for example, the CMR of the standard IA is = 80dB 
while the CMR of the boosted I A is more than 120dB— 
more than a 100-to-l improvement! 



Gain-of-10 
Difference Amplifier 

INA106 




NOTE: You can derive the common-mode drive 
the subregulated supplies from the outputs of 
amplifiers, but it can create problems such as latch-up, 
instability, and reduced performance. 







actual performance boost will depend on matching and 
parasitics in the devices selected. 

Of course, CMR vs Frequency depends on the dynamic 
performance of all amplifiers. Improvement in dynamic CMR 
will be most dramatic when the speed of the amplifiers used 
for A 4 to A ? is much higher than the speed of A l and A 2 . 

HIGH-VOLTAGE IA 

High voltage IAs can also be easily implemented using the 
boosted IA configuration. Standard precision signal level op 
amps can be used for the input amplifiers while the HV chores 
are taken care of by the other (less critical) op amps. The 



FIGURE 6. Boosted Electrometer Instrumentation Amplifier. 



Another dramatic comparison is shown in the scope photos of 
the same IAs using LTC1050 chopper stabilized op amps for 
A, and A y When V QS /dT is critical, chopper stabilized op 
amps may be the best choice — they offer 5|0.V max V QS over 
temperature. As you can see, with a ±2.5 V, 2kHz input signal, 
CMR is limited to =56dB by chopper noise. With the boosted 
circuit, CMR is a respectable =82dB. 

The limit for CMR performance in the boosted IA is the 
difference amplifier. The more gain added ahead of the differ- 
ence amplifier, the better the potential for improvement. For 
example, with a gain of 100V/V ahead of the difference 
amplifier an improvement in CMR of 40dB is possible. The 



simple modifications to the Figure 3 circuit are shown in 
Figure 4. OPA445 op amps are used for A 6 and A, and for the 
difference amplifier, A r To boost the voltage rating of the 
current sources used in the subregulated supplies, two REF200 
current source sections are placed in series. If 1% resistors are 
used for difference resistors R,-R 4 , a pot may be required to 
adjust CMR as shown. The resulting IA will provide outstand- 
ing performance on power supplies up to +45V. 

BOOSTED ELECTROMETER IA 

Electrometer amps depend on the lowest possible input bias 
current. Connecting the input drive circuitry to the IA inputs 
as shown in Figure 2 may result in too much bias current. In 
this case you may want to take the common-mode drive signal 
from the outputs of the input stage as shown in Figure 6. 

Taking the common-mode drive from the outputs of the input 
stage may seem like a good idea, but it creates problems — 
latch-up, instability, and reduced performance. 

Driving the supplies of the input amplifiers from their outputs 
can cause latch-up. Many amplifiers exhibit input phase 
anomalies when their inputs are overloaded or overdirven 
relative to their power supplies. Unless precautions are taken 
when deriving the power supplies from the amplifier outputs, 
these anomalies will result in latch-up conditions. The back- 
to-back 3.3V zener diodes connected to the common-mode 
node (where R 5 and R 6 connect) prevents latch-up by keeping 
the common-mode drive point within 4V of ground. Also, the 
common-mode driven supplies are increased from 5V to 8V. In 
combination, this keeps 4V minimum on the power supplies of 
the input amps eliminating the latch-up condition when using 
the op amps shown. 

The disadvantage of the clamp circuitry is reduced common- 
mode input range. The input common-mode range is limited to 
the clamp voltage of approximately 4V. 

Driving the supplies of the input amplifiers from their outputs 
can also cause insatiably. Driving an op amp's power supply 
pins from the op amp output can cancel the op amp phase 



-160 
-150 
-140 
-130 
£ -120 
rr -110 
O _100 
-90 
-80 
-70 






































































•to* 


*\ 


% 




E 


ioo 


;te 


d 


IA 






















> 






















lec 


ro 


m 


3ter 




\ 
















































..._£ 




























c 


standard 


A 
















































































10 100 1k 10k 
Frequency (Hz) 

NOTE: The boosted electrometer IA circuit adds CMR boost, but the 
boost starts to fall off beyond about 1kHz. 



FIGURE 7. CMR vs Frequency Comparison between 
Standard Three Op Amp IA, Boosted IA, and 
Boosted Electrometer IA. 



compensation and cause the op amp to oscillate. Driving the 
input op amps power supplies through the two-to-one R,, R 6 
divider does not completely cancel the compensation, but it 
does reduce amplifier phase margin significantly. Phase shift 
through A 6 and A, further reduces phase margin. 

You might think that significantly reduced phase margin would 
be acceptable if the input amplifiers are used in high gain. But 
high gain in the differential input/output amplifier depends on 
virtual grounds at both ends of R G . At the unity gain frequency 
of the op amp, where instability occurs, loop gain disappears and 
the op amps no longer approximate the ideal. At best, the op 
amps operate in a noise gain of two — the op amps must be stable 
in a gain of two. That's why you can get in trouble trying to use 
decompensated op amps in the front-end of an IA. 

Using the faster OPA2107 for A 6 and A, along with the OPA128 
electrometer op amp for A, and A 2 results in good stability. 
The improvement of CMR is shown in the CMR vs Frequency 
plot, Figure 7. The plot compares a standard IA (using the 
OPA128 and an INA106) to the Figure 2 and Figure 6 boosted 
IA circuits. The boosted circuits give a 30dB (better than 30/ 
1) improvement in CMR up to about 1kHz. Beyond 1kHz, the 
CMR vs Frequency of the Figure 6 circuit begins to fall-off. 
At 10kHz, the Figure 6 circuit only offers about a six-to-one 
improvement. 

LAYOUT 

To get the best performance from the boosted IA, use a good 
printed circuit layout. For best CMR, keep the signal-path 
circuitry symmetrical. A printed circuit layout of the complete 
boosted IA circuit, Figure 2, is shown in Figure 8. It produced 
the excellent results shown in this bulletin. Notice that good 
signal-path symmetry is achieved even though a single-sided 
layout is used. 



»~ r C4 I - inrn 

■ ■ Q_C£ 




j i 



s 



REF 

200 



J2 



Z 



V 



m 



i — i 



R3 




Best performance depends on signal-path symmetry. Notice that excellent 
symmetry can be maintained even with single-sided board layout. Extra 
pads at RFB allow stacking of feedback capacitors. 



FIGURE 8. Printed Circuit Layout of Figure 2 Boosted IA. 



■""^"^ APPLICATION BULLETIN 9 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



IMMI 



INPUT FILTERING THE INA117 +200V DIFFERENCE AMPLIFIER 



By R. Mark Stitt (602) 746-7445 



Many customers have asked how to add input filtering to the 
INA1 17. Since the INA1 17 is rated for±200V input voltage 
(±500V without damage), it is commonly used in environ- 
ments with very high input noise or with high-voltage input 
transients. This bulletin shows how to connect input filters, 
discusses the errors they can add, and shows how to elimi- 
nate the errors. 

Figure 1 shows the connection of a differential input filter. 
A pole is formed by C x and the two external input resistors. 
f-3dB = 1/(4 • rt • Ri • C,). Differential input filtering is pre- 
ferred because mismatches in filter components do not 
degrade CMR. 

DON'T USE COMMON-MODE 
INPUT FILTERS ALONE 

Don't be tempted to use common-mode input filtering alone 
(Figure 2) unless you are prepared to carefully match com- 
ponents. Mismatches between the R ( • C 2 time constants 
reduce AC CMR. The mismatches result in a differential 
input signal in response to AC common-mode inputs. Even 
if you successfully match the components for good AC 
CMR at room temperature, maintaining the match over 
temperature can be a problem. 

A COMBINATION COMMON-MODE 

AND DIFFERENTIAL INPUT FILTER IS OK 

If you want common-mode input 
tion with differential input 



use it in conjunc- 
as shown in Figure 3. If 



2kt2 



R, 

380ka 



R 2 
380kn 



R 3 

380k£2 



21.1kQ- 




INA117 



A differential pole is formed at: 

'-3dB = 1/(4*ifR|-C,) 
AC CMR is not degraded by a differential input filter. 



FIGURE 1. INA1 17 with Differential Input Filter. 




INA117 



-O 

Vn 



AC CMR will be de- 



FIGURE 2. INA117 with Common-Mode Input Filter. 



2kQ 

o-VW^ 



R, 

v 3 

0.01 uF- 



c, 

4.7uF 



380k£2 



380kfl 



380kD 




"5 - 

2f.fkfl- 



.2o.okn 



INA117 



If Ci » C 2 , AC common-mode errors due to R| • C2 mismatches will be 
shunted by C1, improving AC CMR. 



FIGURE 3. INA117 with a Combination Differential and 
Common-Mode Input Filter. 

Q » C 2 , AC common-mode errors will be shunted by Q 
so AC CMR can be successfully boosted. A value of 
C[ = 500 • C2 is suggested. 

Figure 4 shows actual CMR vs Frequency performance plots 
for the Figure 2 and Figure 3 circuits. Standard INA117 
performance is shown for comparison. The standard INA1 1 7 
has about 60dB CMR at 30kHz. Mismatches of 5% in R • C 
time constants (5% C 2 mismatch) cause the Figure 2 circuit 
CMR to drop below 60dB at less than 200Hz. Adding a 



0) 

"5 
m 

c 
o 

33 
(0 
O 

Q. 
< 



e 1991 Burr-Brown Corporation 



AB-029 



Printed in U.S.A. March, 1991 




100 



1k 

Frequency (Hz) 



10k 



100k 



FIGURE 4. CMR vs Frequency Plots for Figure 2 and 3 
Circuits with Standard INA1 17 for Comparison. 

4.7uF differential input filter capacitor shunts out common- 
mode filter errors producing greater than 70dB CMR to 
100kHz as shown in the plot of Figure 3's performance. 

INPUT RESISTORS CAN REDUCE DC CMR 

Notice that the DC CMR of the Figure 3 circuit is reduced 
from =92dB to =82dB. The CMR reduction is due to 
mismatches from input filter resistors, R T . 

CMR in the INA1 17 depends on close resistor ratio match- 
ing. For errors in R, and R 3 : 

CMR = -20 Log(%/105) 

Where: 

CMR = CMR for errors in R, or R 3 [dB] 
% = the error in R, or R 3 [%] 

The number, 105, in the denominator comes from R,, R 3 
sensitivity equations. 

s|[™ =±R,/(R I + R 4 ) 

For example, % = 0.002% is required for the typical 94dB 
INA117 CMR. 

Even though the 2kfl input resistors are relatively small 
compared to the 380kI2 input resistors in the INA117, mis- 
matches will reduce CMR. Even if perfectly matched external 
input resistors are used there can still be problems with CMR. 

Although some resistor ratios in the INA117 are carefully 
matched to achieve good CMR, the R,/R 3 ratio is not. A 
typical mismatch of 1 % can be expected. The effect is to add 
an effective 1 % mismatch to external resistors. The follow- 
ing worst-case CMR can be expected: 

CMR = -20 Log((ERROR, + ERROR 2 )/105) 
Where: 

ERROR, = Error due R h R,, and R 3 mismatches [%] 
ERROR, = R t • (T OL + 1)/(R, + 3.8 • 10 5 ) 
R, = DC resistance of external filter resistor, R,, [f2] 
T 0L = Tolerance of R, [%], i.e. 1.0 for 1% 
ERROR 2 = Initial INA1 17 error [%]— See Table I 



NNrt 1 1 /DM typ 


at 


U.UU£ 


INA117BM min 


86 


0.005 


INA117KP min 


70 


0.033 



TABLE I. Initial INA117 CMR Values. 





ERROR, 


ERROR 2 


CMR 


(") 


(%) 


(%) 


(dB) 


1k 


0.005 


0.005 


80 


2k 


0.010 


0.005 


76 


5k 


0.026 


0.005 


71 


10k 


0.051 


0.005 


65 



TABLE II. Examples of Worst-Case CMR to be Expected 
(INA117BM and selected 1% R,s). 



105 



Also, 

ERROR 2 = - 10(CMRii7/20) 

CMR„ 7 = Initial INA117 CMR [dB] 
See Tables I and II for examples. 

CMR TRIM 

If you want to use 10k£2 input resistors and must be assured 
of good DC CMR, you can use the trim circuit shown in 
Figure 5. Resistor TCR mismatches can limit difference 
amplifier performance over temperature. Use high quality 
film resistors and keep R T < 10k£2 for good performance 
over temperature. 



R, 

10k£2 

o-VW- 

V 2 



10ki2 



c, 



380k£2 

-m- 



R 3 

380k£i 



380k£2 



"5 - 

21.1k£2- 




INA117 



20on 

' — vYVM CMR Trim 



FIGURE 5. INA1 17 with Differential Input Filter and CMR 
Trim. 



ADDED INPUT RESISTORS CAUSE GAIN ERROR 

Adding input resistors to the INA117 causes gain error. 
When all resistor ratios are properly adjusted for good CMR, 
INA1 17 gain is R^. When input filter resistors are added, 
gain is reduced to R^CRi + Ri). With R[ = lOkQ, gain is 
=0.974 V/V (approximately -2.6% gain error). Since gain 
does not depend on R 3 , R 4 , or R 5 , the gain error can not be 
corrected by adding resistance in series with any pin. 

CORRECTING GAIN ERROR 

To correct for the gain error introduced by the input filter 
resistors, you can add a small amount of positive feedback 
as shown in Figure 6. Resistors R 4A , R 4B , and R 5A must be 
selected to maintain CMR and to give the proper positive 
feedback to correct for gain error. 

The following procedure is suggested: 
Set 



R 4A = 10Q 



This is an arbitrary but adequate value for R 4A . It is the 
smallest standard 1% value. With this small value, even a 
5% ratio matching error between R 4A and R 5A would only 
degrade INA117 CMR to 82.5dB. In practice, ratio errors 
will be lower than this when closest standard 1% resistors 
are used. 

Calculate R 4B and R 5A and use closest standard 1% resistor 
value. 

19 • R 2 • R 4A 



R 4B = 18-R 4A + 



R. 



With R, < lOkQ and R 4A = 10Q this is an adequate ap- 
proximation for all practical purposes. 



R, 
iokn 

o——J\/\A- 

v, 



c, 



iokn 



Ri 

380kQ 

-vW- 



380k£J 



R 3 

30k 

r 5 : 

21.1kQ" 



R 2 
380k£J 

WW- 



1 




INA117 



-o 

Vr, 




™4B 

" 4 * 7.32k£J 
10£2 



FIGURE 6. INA1 17 with Differential Input Filter and Posi- 
tive Feedback Circuit to Compensate for Gain 
Error Due to Rj. 



If R 2 = 380k£2, R, = 10k£2, and R 4A = 10Q: 
ion . 72Mft 



Ri 



= 7.4kQ 



, use 7.32kQ 



361 • R 2 • R 4A • R 4B 



324(R 2 • R 4A ) + 324(R 2 • R 4B ) - 342(R, A • R 4B ) 

With R 2 = 380k£2 and R 4A = 10Q: 

3.61 • R 4B 



Rsa = 



3.24 + 0.323991 • R 4B 



With R 4B = 7.4kft, R 5A = 1 1 . 1 3Q , use 1 1Q. 



FINE-TRIM FOR ZERO GAIN ERROR 

You must trim to get zero gain error. The resistors in the 
INA1 17 are accurately ratio trimmed to give excellent CMR 
and gain accuracy, but their absolute values are only accu- 
rate to within about +20%. With the values calculated above, 
gain error will be reduced from approximately -2.6% to 
about +0.5%. 

For lower gain error use the gain-trim circuit shown in 
Figure 7. The circuit is the same as in Figure 6 except, R 4B 
is replaced with a 5kQ fixed resistor and a 5kQ pot. 

To trim for zero gain error, ground the INA117 inputs (0V 
input) and measure the offset voltage, V 0FF , at the output. 
Apply a known input voltage, V REF , (e.g. 10.0V) to the 
INA1 17 noninverting input. Measure V REF so you know its 
precise value. Adjust the 5kQ pot for the correct INA117 
output voltage: V oux = V REF + V 0FF . 



R| 
iokn 



c, 



R, 

10kQ 



R, 

380kS2 



R 3 

380kQ 



R 5 : 

21.1kQ- 



R 2 
380kQ 




:20.0kQ 



INA117 



5kQ 5kQ 




— Mh^ 



Gain Trim 



FIGURE 7. INA1 17 with Differential Input Filter and Gain 
Trim Circuit. 



10k£2 

^2 



10kQ 

v 3 



380kn 



380kQ 



R 5 : 

21.1W2- 



380kn 




CMR Trim 



.20.0k£! 



INA117 




5k£2 5kn 

Hw — m — 

^4A I 



Gain Trim 



FIGURE 8. INA1 17 with Differential Input Filter and Both 
Gain Trim and CMR Trim Circuits. 



You can automate the trim process by using an amplifier 
with a known gain of 1V/V. The Burr-Brown INA105BM 
difference amplifier with gain error = ±0.01 % max is a good 
choice. Instead of using a voltage reference, drive the input 
of the INA1 17 with a +5V, 10Hz sine or triangle wave (see 
AN-165, Fig. 46 for a suitable triangle generator circuit). 
Connect one input of the INA105 to the driven INA117 
input. Connect the other input of the INA105 to the INA1 17 
output. Adjust the 5kQ gain trim pot for zero AC at the 
INA105 output. Using the AC technique allows you to 
distinguish between offset and gain error. 

If you want to adjust both gain and CMR, use the circuit 
shown in Figure 8. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



4-20mA TO 0-20mA CONVERTER AND 
CURRENT SUMMING CURRENT-TO-CURRENT CONVERTERS 

By R. Mark Stitt and David Kunst (602) 746-7445 



Current loops have become the standard for signal transmis- 
sion in the process control industry. Current loops are 
insensitive to noise and are immune to errors from line 
impedance. Burr-Brown offers a complete line of monolithic 
4mA to 20mA current loop transmitters and receivers. 

XTR101 

General purpose two-wire 4-20mA current-loop transmitter. 
This transmitter has an instrumentation amplifier input and 
two 1mA current sources for transducer excitation and 
offsetting. 

XTR103 

Two-wire RTD 4-20mA current-loop transmitter. Similar to 
XTR101, but with internal linearization circuitry for direct 
interface to RTDs (Resistance Temperature Detectors). The 
XTR103 along with an RTD forms a precision temperature 
to 4-20mA current loop transmitter. 

XTR104 

Two-wire bridge 4-20mA current-loop transmitter. Similar 
to XTR101, but with shunt regulator and linearization cir- 
cuitry for direct interface to resistor transducer bridges. 

XTR110 

Three- wire 4-20mA transmitter. The XTR1 10 converts a 0- 
5V or 0-10V high-level input into a 0-20mA or 4-20mA 
current-soruce output. 

RCV420 

Self-contained 4-20mA receiver. Conditions and offsets 4- 
20mA input signals to give a precision 0-5V output. Con- 
tains precision voltage reference, 15Q precision sense resistor 
and ±40V common-mode input range difference amplifier. 

The 4mA to 20mA current loop is the most often used 
standard. Since the minimum signal current is 4mA, the 
transducer and transmitter can be powered by the same two 
wires used for the current loop connection. This feature 
eliminates the need for a remote power supply. Also, open 
circuits are easy to detect since the signal goes to 0mA. 
Some systems, however, use a to 20mA current loop 
standard instead. To interface to these systems, the 4-20mA 
XTR output must be converted to 0-20mA. This bulletin 



R 2 



'OUT 

o— 




A, 



-vW- 



tauT = -I in ' fV R 1 

NOTE: The minus sign in the equation means that the i IN , I ut currents 
flow as shown. 



FIGURE 1. Basic Inverting Current-to-Current Converter. 

shows the suggested circuit and also discusses summing 
current-to-current converters in general. 

INVERTING CURRENT-TO-CURRENT 



Figure 1 shows the basic inverting current-to-current con- 
verter. The input current all flows through R 2 resulting in an 
I IN • R 2 voltage drop across R 2 . The op amp forces the same 
voltage across R, so that there is no voltage difference at the 
op amp inputs. The Iqut current is therefore: 

For Figure 1 : 



Notice that, like its cousin the inverting voltage amplifier, 
the 



itput current can be greater than or less than the input 



R 2 



'out 
O— 




A, 



In 



• In) FVRi 



NOTE: The minus sign in the equation means that the l !N , I 0U t currents 
flow as shown. 



CO 
i_ 

.Q 



c 

I 

3 
ffi 

C 

o 



Cl 
Dl 
< 



FIGURE 2. Equal-Gain Summing Inverting Current-to- 
Current Converter. 



® 1 99 1 Burr-Brown Corporation 



AB-031 



Printed in U.S.A. April. 1991 




Iout = -It • FyRi - l 2 (R 2 + R 3 )/Ri l N (R2 + R3 + "• + RnVRi 

NOTE: The minus sign in the equation means that the l IN , Iout currents 
flow as shown. 



'OUT — 'INV t ^y^v 
Notice that, like its cousin the noninverting voltage ampli- 
fier, the gain is always greater than 1.0 so that the output 
current must always be greater than the input current. 

As with the inverting summing current-to-current converter, 
so long as the gain is the same, any number of currents can 
be summed at the current-to-current converter input as 
shown in Figure 5. 

For Figure 5: 

Iout = fli + h + — + WO + R2/R1) 



FIGURE 3. Arbitrary-Gain Summing Inverting Current-to- 
Current Converter. 

current. Of course, the output can also be equal to the input 
so the circuit can be used as a unity-gain current inverter 
with R, = R 2 . 

So long as the gain is the same, any number of currents can 
be summed at the current-to-current converter input as 
shown in Figure 2. 

For Figure 2: 

lour = Hi ~h WR2/R1 

Any number of currents can be summed with arbitrary gain 
by using separate gain-setting resistors as shown in Figure 3. 

For Figure 3: 

Iout = -Ii • R2/R1 - h<*2 + RsVRi ~ ~ 
I N (R 2 + R 3 + ••• + R N )/R, 



NONINVERTING CURRENT-TO-CURRENT 
CONVERTERS 

Figure 4 shows the circuit for the basic noninverting current- 
to-current converter. As before, all the input current flows 
through R 2 resulting in a I IN • R 2 voltage drop across R 2 . In 
this circuit, the op amp is connected as a unity-gain buffer 
forcing the same voltage drop across R,. The output current 
is the sum of the input current flowing through R 2 and the 
current flowing through R,. The following relationships apply 
to the noninverting circuits. 




FIGURE 4. Basic Noninverting Current-to-Current 
Converter. 




bur - Ci + 'a + — + "n)(1 + R2/R1) 



FIGURE 5. Equal-Gain Summing Noninverting Current- 
to-Current Converter. 

Likewise, any number of currents can be summed with 
arbitrary gain by using separate gain-setting resistors as 
shown in Figure 6. 

For Figure 6: 

Iout = W + Ra/Ri) + ^(Ri + R 2 + RsVRi + ~ + 
I N (R, + R 2 + R 3 + ••• + Rn)/Ri 




Iout = M1 + R2/R1) + WRi + R2 + R3VR1 + — + 
l N (R, + R 2 + R 3 + •« + R N )/R, 



FIGURE 6. Arbitrary-Gain Summing Noninverting Current- 
to-Current Converter. 



85 



INVERTING AND NONINVERTING 
CURRENT-TO-CURRENT CONVERTERS 

The inverting and noninverting circuits can be used simul- 
taneously either with equal gains or arbitrary gains as shown 
in Figures 7 and 8: 

For Figure 7: 

'OUT = (Ml A _ ^2A _ _ Ina)R2a/Rib) + 
{(I 1B + I 2B + + Inb)0 + R2B/R1B)) 




'OUT = {HlA - l2 



' - Ina)R2a/R 1B ) + {(lis + I2B + — + Inb)(1 + R 2B /Rib)} 



FIGURE 7. Equal-Gain Summing Inverting and 
Noninverting Current-to-Current Converter. 

For Figure 8: 

loUT = MlA * R 2a/RiB - I2A( R 2A + R 3a)/RiB ~ *"* ~ 

Ina(R2a + Rba + + Rna)/Rib) + 
{I, B (1 + R 2b /Rib) + I 2 b(Rib + R2B + R3b)/Rib + — + 
Inb(Rib + R 2B + R3B + *** + RnbVRib) 



Rna fc R3A R2A 




'OUT = HlA * R2A/R1B- '2A<R2A + R3a)/Ri B - - 

'na(R2a + R3A + + Rna)/Rib1 + 
{l 1B (1 + R 2 b/Rib) + '2b(Rib + R2B + RsbVRib + •" + 
Inb(R,b + Rjb + R3B + + Rnb)/R,s} 



8. Arbitrary-Gain Summing Inverting and 
Noninverting Current-to-Current Converter. 



4-20mA to 0-20mA CONVERTER 

There are two ways to make a 4-20mA to 0-20mA converter 
using current summing circuits and a REF200 lOOuA cur- 
rent source for offsetting. Since the polarity of the 0-20mA 
output current must be the same as the 4-20mA input signal, 
the noninverting circuit is used in the main signal path. The 
REF200 100(iA current source can be connected in either 
polarity so either inverting or noninverting summing can be 
used to offset the signal for OmA out with 4mA in. 

4-20m A to 0-20m A CONVERTER USING BOTH 
INVERTING AND NONINVERTING CURRENT-TO- 
CURRENT CONVERTER CIRCUITS 

One implementation of the 4-20mA to 0-20mA converter is 
shown in Figure 9. From the Figure 4 and Figure 1 equa- 
tions: 

For Figure 9: 

Iout = Ii(1 + R2/R1) - I2 • R3/R1 

Where: 

i! = 4-20mA input current 

I 2 = 100|xA REF200 offsetting current 

Two equations can be written: one for lour = OmA with Ii N 
= 4mA and one for Iqut = 20mA with I [N = 20mA. Since 
there are three unknowns (R 1; R 2 , and R 3 ) and only two 
equations, one resistor value must be selected first. A value 
of 100£2 was selected as an arbitrary but adequate value for 
R 2 . With R 2 = 100Q, the maximum voltage drop across it is 
2V at 20mA. A smaller value for R 2 will reduce the voltage 
burden and power dissipation in the circuit, but since the 
signal-to-noise ratio is reduced, it will be more sensitive to 
op amp errors. 

To solve for R^ 

Notice that the current gain is: 

(20mA - 0mA)/(20mA - 4mA) = (20mA)/(16mA) 
= 1.25mA/mA 

Rewriting the Figure 4 equation in terms of gain: 

GAIN = Iout/Iin 
GAIN = 1 + R2/R, 

Solving the gain equation for R x : 

Ri = REGAIN - 1) 

Substituting R 2 = 100Q: 

R[ = 1000/(1-25 - 1) 
Ri = 400Q 

Then, solving the Figure 9 equation for R 3 : 

R 3 = I,(R! + R 2 )/I 2 

Substituting Ij = 4mA, I 2 = lOO^A: 

R 3 = 40(R, + R 2 ) 

Substituting R, = 100£2, R 2 = 400Q: 

R 3 = 20.0kQ 



O.OIuF 




4mA to 20mA In 



0mA to 20mA Out I ^ 1 Source 
* v out 



NOTE: This circuit has poor compliance with positive power-supply rail. 



FIGURE 9. 4-20mA to 0-20mA Current-to-Current 
Converter Using Inverting and Noninverting 
Summing Circuits. 



-v,o- 



i, o- 




4mA to 20mA In 



100Q- 



0.01 pF 



0mA to 20mA Out 



I Source 

V OUT 



NOTE: This circuit has excellent compliance with positive power-supply 
rail. 



FIGURE 10. 4-20mA to 0-20mA Current-to-Current 
Converter Using Only Noninverting Summing 
Circuits. 



4-20m A TO 0-20m A CONVERTER USING ONLY 
NONINVERTING CURRENT-TO-CURRENT 
CONVERTER CIRCUIT 

The other possible circuit is shown in Figure 10. From the 
Figure 6 equations: 

For Figure 10: 

t out = + R2/R1) + l2(Ri + R2 + R3VR1 
Where, as before: 

11 = 4-20mA input current 

1 2 = 100U.A REF200 offsetting current 

The relationships for R t and R 2 are the same as for the 
Figure 9 circuit: with R 2 = 100Q, R, = 400Q. 

Solving the Figure 10 equation for R 3 : 

R 3 = (It - I 2 )(R, + R 2 )/I 2 

Substituting I, = 4mA, I 2 = 100U.A: 

R 3 = 39(R, + R 2 ) 

Substituting R x = 100Q, R 2 = 400Q: 

R 3 = 19.5kTi 

WHICH 4-20mA TO 0-20mA 
CONVERTER IS BETTER? 

The only significant functional difference between the Fig- 
ure 9 and Figure 10 converter circuits is the output voltage 
compliance range. Output range of the current-to-current 
converter circuit is limited by the op amp input and output 
ranges and by the minimum compliance range of the REF200 
current source. Voltages for the two circuits at the 0mA and 
20mA output current extremes are shown in Table L 



OUTPUT 


FIGURE 9 CIRCUIT 


FIGURE 10 CIRCUIT 


CURRENT 


OP AMP V m 


OP AMP V 0UT 


OP AMP V IN 


OP AMP V 0lrr 


0mA 


0.4 


-1.6 


-1.56 


-1.56 


20mA 


2.0 


0.0 


0.04 


0.04 


NOTE: With the 0-20mA output connection node held at 0V. 



TABLE I. Op Amp Input/Output Voltages for Figures 9 
and 10 Circuits. 



Both circuits have an op amp V 0UT of approximately -1.6V 
at one extreme. This limits the compliance to the negative 
power-supply rail to SL + 1.6V where SL is the op amp 
output negative swing limit. For example, if an op amp can 
swing to -12V (V s = ±15V), its swing limit is SL = 3V. The 
closest the circuit can swing to the negative rail is 3V + 1.6V 
= 4.6V or V OUT = -10.4V (V s = ±15V). 

The Figure 10 circuit has an advantage for compliance to the 
positive power-supply rail. The Figure 9 circuit has a worst- 
case Vjn = 2V. Also, the REF200 (with a min compliance of 
2.5V) is connected between the input and +V S . This limits 
the compliance to the positive power-supply rail to 2V + 
2.5V = 4.5V. 

The Figure 10 circuit has a worst-case V IN = 0.04V. Also, 
the REF200 is connected between the input and -V s . This 
allows the Figure 10 circuit to swing to the positive power- 
supply rail within the limits of the op amp input compliance. 
Op amps are available with input compliance to +V S . 
Compliance of the Figure 10 circuit (using the OPA1 77) is: 

+13V (+14V typ), -10.9V (-11.4V typ) with V s = +15V. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR -BROWN® 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 

IC BUILDING BLOCKS FORM COMPLETE 
ISOLATED 4-20mA CURRENT-LOOP SYSTEMS 



8; 



By R. Mark Stitt and David Kunst (602) 746-7445 



Current loops have become the standard for signal transmis- 
sion in the process control industry. Current loops are 
insensitive to noise and are immune to errors from line 
impedance. Adding isolation to the 4-20mA current loop 
protects system electronics from electrical noise and tran- 
sients. It also allows transducers to be electrically separated 
by hundreds of volts. Burr-Brown now offers all of the 
integrated circuit building blocks needed to assemble com- 
plete isolated 4-20mA current-loop systems. The product 
line includes two-wire transmitters, two-wire receivers, low 
cost isolation amplifiers, and low cost isolation power sup- 
plies. Three two-wire transmitters are available: one is 
general purpose, one designed for use with RTD tempera- 
ture sensors, and one designed for use with bridge circuits. 

THE BASIC ISOLATED 4-20mA 
TWO-WIRE SYSTEM 

Figure 1 shows a typical isolated 4-20mA system. An 
XTR101 converts a position sensor output into a two-wire 
4-20mA current-loop signal. An ISO 122 low-cost isolation 
amplifier isolates the 0-5V signal. Power (±15V for the 
RCV420, 30V for the current loop) is supplied by the 
HPR1 17 low-cost DC/DC converter. 

In this example, a Penny & Giles Model HLP 190 50mm 
linear potentiometer is used as the position transducer. One 
of the 1mA current sources in the XTR101 is used to bias the 
transducer. A 2kQ fixed resistor in parallel with the 2kQ 
potentiometer sets its output range to 0-1V. The 2.5k£2 
resistor sets a 5V common-mode input level to bias the 
XTR101 instrumentation amplifier input into its linear re- 
gion. 

With the span-setting resistor connections open, the XTR101 
current-loop output is: 

I = 4mA + V 1N /62.5Q 

Where: 

I = current loop output (A) 
V, N = Differential IA input voltage between 
pins 3 and 4 (V) 

The XTR101 directly converts the 0-1V position sensor 
output into a 4-20mA current loop output. The isolated 
voltage output from the ISO 122 is 0-5 V for 0-50mm dis- 
placement. 

Other, more specialized two-wire transmitters are also avail- 
able. See the brief summary at right of available building 
blocks. 



HPR117 LOW-COST ISOLATED DC/DC CONVERTER 

Provides ±15V, 30mA isolated output power with 15V 
input. Key specifications are: 
±V ut= V IN , ±5% 

(V IN = 13.5V to 16.5V, I OUT = 25mA) 
I oux = 30mA continuous at 70°C. 
8mA quiescent current, no load; 80% efficiency, full load 
750VDC isolation rating 

IS0122 LOW-COST PRECISION ISOLATION AMPLIFIER 

Precision analog isolation amplifier in a standard 16-pin 

plastic DIP. Key specifications are: 

Unity gain (±10V in to +10V out), ±0.05% 

0.02% max nonlinearity 

5mA quiescent current 

140dB isolation mode rejection at 60Hz 

1500Vrms continuous isolation rating (100% tested) 

RCV420 

Self-contained 4-20mA receiver. Conditions and offsets 
4-20mA input signals to give a precision 0-5V output. 
Contains precision voltage reference, 75f2 precision sense 
resistor and ±40V common-mode input range difference 
amplifier. The RCV420 has a total combined span and zero 
error of less than 0.1% — adjustable to zero. 

XTR101 

General purpose two-wire 4-20mA current-loop transmitter. 
This transmitter has an instrumentation amplifier input and 
two 1mA current sources for transducer excitation and 
offsetting. 

XTR103 

Two-wire RTD 4-20mA current-loop transmitter with 9V 
compliance. Similar to XTRlOl, but with internal lineariza- 
tion circuitry for direct interface to RTDs (Resistance Tem- 
perature Detectors). The XTR103, along with an RTD, 
forms a precision temperature to 4-20mA current-loop trans- 
mitter. Along with an RTD, the XTR103 can achieve better 
than 0. 1 % span linearity over a -200°C to +850°C tempera- 
ture span. 

XTR104 

Two-wire bridge 4-20mA current-loop transmitter with 9V 
compliance. Similar to XTRlOl, but with shunt regulator 
and linearization circuitry for direct interface to resistor 
transducer bridges. The XTR104 can provide better than 
0.1% span linearity from bridges with uncorrected linearity 
in excess of 2%. 



1991 Burr-Brown Corporation 



AB-032 



Primed in U.S.A. June, 1991 




o.oiuFrz 



NOTE: Position sensor is Model HLP 190 
50mm available from Penny & Giles Controls, 
Inc., 35 Reynolds St., Attleboro, MA 02703, 
(508)226-3008. 



0.01IJF 



FIGURE 1 . Four IC Packages and Transducer Form Complete Isolated 4-20mA Current-Loop System. 



THERMISTOR-BASED 
TEMPERATURE MEASUREMENT 

The most often measured physical parameter is temperature. 
Of the many commonly used temperature measurement 
transducers, the thermistor is the least expensive. Both 
positive and negative temperature coefficient types are avail- 
able in all sorts of packages. Due to their high temperature 
coefficients, negative temperature coefficient types are the 
most common and widely used types. Thermistors are useful 
for temperature measurement from -55°C up to 300°C. 



Figure 2 shows the circuit for a thermistor-based two- wire 4- 
20mA current-loop temperature measurement system. A 
bridge is formed with a thermistor, R T i, and a 5kQ variable 
resistor. The bridge is excited by the two 1mA current 
sources in the XTR101. The 5kQ variable resistor is used to 
set the temperature-range zero for 4mA current loop output. 
The XTR101 span setting resistor, R s , sets the span to get 
20mA current-loop output at full-scale. XTR101 current- 
loop output is: 

I = 4mA + V^O + 2500Q/R S )/62.5Q 



10 



o.oiuFqr 



11 




1mA 



XTR101 



e- 



1mA 



e- 



5kh J 




V+ 



'out 



4-20mA Out 



Zero Adjust 



FIGURE 2. Basic Thermistor-Based Two-wire Temperature Measurement Using XTR101. 



89 



v+ 



16 



_ 300kll 
■75Q 



-75£2 



-V s 300k£2 



RCV420 



92k£2 



ma 




11.5kn 



10CW} 



10.0V 
Ref 



~p3 |5~ 



12 



15 



14 



10 



6 5 4 

OOP 



0-5V 



"hpaitT 



fGndV w 
K Input 
/ Section 
|v+ V- 



if 



1S0122P 



MM 



V- v+ 

Output 
Section 



— im 



-Q+15V 



-0-15V 



-O Output 
Gnd 

-ov 

0-5V 



Where: 

I = Current loop output (A) 

V IN = Differential IA input voltage between pins 3 and 4 

(V) 

R s = Span-setting resistor (Q.) 

Keep in mind that the maximum differential input range for 
the XTR101 is IV. 

Since the thermistor is a powered sensor, self heating can be 
a problem. For example, with a thermistor voltage of 5V, 
power dissipation is 5V • 1mA = 5m W. If a bead-in-glass 
type thermistor with a thermal resistance of 600°C/W is 
used, self-heating can increase the thermistor temperature by 
3°C. To minimize this error, use a thermistor in a low 
thermal resistance package or lower the thermal resistance 
by heat sinking the thermistor to a thermal mass residing at 
the temperature to be measured. For example, if air tempera- 
ture in an enclosure is to be measured, attach the thermistor 
to the package instead of mounting it in free air. 

THERMISTOR-BASED LIQUID LEVEL INDICATOR 

Due to high nonlinearities, thermistors can only be used for 
accurate temperature measurement over relatively small 
temperature spans. The high output of thermistors, however 
makes them attractive for other applications. In some appli- 
cations thermistor self-heating can be used to advantage. 
Consider, for example, the liquid level indicator shown in 
Figures 3A and 3B. A bridge is formed by a pair of matched 
thermistors. The bridge is excited by the 1mA current 
sources in the XTR101. When both thermistors are sub- 
merged in liquid as shown in Figure 3A, the thermistors are 



at the same temperature — heat-sinked by the liquid. The 
potentiometer, R 3 , is used to correct for component toler- 
ances and zero the bridge for 4mA current-loop output. 

When the liquid level falls below thermistor R T i as shown in 
Figure 3B, the temperature of R T i increases due to self- 
heating. The resulting bridge imbalance is measured by the 
XTR. Span-setting resistor, Rs, is selected to give 10mA 
output under low liquid level conditions. There is no simple 
rule for selecting R s . Its value depends on thermistor selec- 
tion and liquid properties and conditions. 

When compared to level detectors using floats and moving 
parts, a thermistor-based liquid level indicator can have 
much better reliability. 

GAS FLOW MEASUREMENT 
USING THERMISTORS 

The liquid level indicator uses thermistor self-heating for a 
two-state high/low measurement. The gas flow measure- 
ment system shown in Figure 3C gives a quantitative flow 
rate measurement. 

As in the previous example, a matched thermistor bridge is 
biased by the two 1mA current sources in the XTR101. One 
thermistor is positioned in the air flow stream. The other 
thermistor resides in still air — baffled from the air stream. 
The thermal resistance of the thermistor is proportional to 
the air flow rate. Potentiometer, R 3 , is used to balance the 
bridge for 4mA out at zero flow rate. Span setting resistor, 
R s , is selected to give a full-scale 20mA output at maximum 
flow rate. The value of R s depends on thermistor character- 
istics and gas flow dynamics. 





FIGURE 3B. Thermistor-Based Two-wire Liquid Level Detector Using XTR101. 



91 



XTR101 



e- 




FIGURE 3C. Thennistor-Based Air Row Rate Measurement Using XTR101. 



Many systems today use resistance wire instead of ther- 
mistors for gas flow rate measurement. These are sometimes 
called hot-wire anemometers, and can have faster response 
due to lower (thermal mass)/(heat transfer) ratio. 

DIODE-BASED TEMPERATURE MEASUREMENT 

Cousin to the thermistor is the semiconductor diode tem- 
perature transducer. Regular silicon diodes, biased with 
constant current, have a forward voltage of about 0.6V with 
a temperature coefficient of about -2mV/°C. The usable 
upper temperature range for silicon semiconductors is about 
125°C. Some high-temperature types are useful up to 200°C. 
In the future, novel semiconductor types such as silicon 
carbide and diamond promise to raise the upper usable 
temperature range of semiconductors into the 300°C to 
600°C range. For now, thermocouples and RTDs can be 
used for higher temperature measurements. 

Consider semiconductors for measurement of very low tem- 
peratures. Specialized silicon diodes can be used at very low 
temperatures. For example, the LakeShore Cryotronics, Inc., 
DT-470 series silicon diode cryogenic temperature sensor 
can be used to measure temperatures near absolute zero — 
from 1.4Kto475K. 



Figure 4 shows a cryogenic temperature measurement cir- 
cuit using a silicon diode temperature sensor. The sensor 
requires an accurate lOuA current source for excitation. One 
of the current sources from the XTR101 is scaled by a 
precision mirror to supply the lOuA excitation current. 

To convert a 1mA current-source output into a precise lOuA 
for sensor excitation, a precision current mirror is formed 
with R 2 , R 3 , and A,. The 1mA current source is connected 
to R 2 and the inverting input of the op amp. The op amp 
drives its inputs to the same voltage through R 3 . The result 
is a precision 0. 1 V across both R 2 and R 3 . The output current 
at the nonin verting input is 1mA • R2/R3 = 10|iA. With the 
amplifier specified, op amp bias currents add negligible 
error. 

The other 1mA current source in the XTR101 supplies both 
a precision zero-set voltage and power for the op amp. The 
current source is connected to a 5.1V zener through Rj. The 
current through R) is precisely 1mA - 10|iA. Zero-set 
voltage is Ri • 990uA. The 5.1V zener sets the supply 
voltage of the op amp. The 249k£2 resistor in series with the 
temperature sensor diode forces the op amp to operate in its 
linear common-mode and output ranges. 



0.01 uF 




NOTES: 

1) Select span-setting resistor for desired output 
range— see text. 

2) Cryogenic silicon diode temperature sensor. 
LakeShore Cryotronics, Inc., 64 Walnut St., 
Westville, Ohio 43081, (614)891-2243. 



FIGURE 4. Silicon-Diode-Based Cryogenic Temperature Measurement System Using XTR101. 



OTHER SILICON TEMPERATURE SENSORS 

Although diodes are common in temperature measurement 
applications, their accuracy is limited. The temperature co- 
efficient of a silicon diode has a nonlinearity of about 1% 
over a 0-100°C temperature span. Also, the stability of the 
forward voltage with time is limited. 

Better accuracy can be obtained from silicon diodes by 
measuring the difference in forward voltage drops between 
diodes operating at different current densities. This voltage 
has a positive temperature coefficient proportional to abso- 
lute temperature. If the diodes have low bulk resistance and 
are well-matched, temperature coefficient linearity of better 
than 0.01% is possible. 

THERMOCOUPLE-BASED 
TEMPERATURE MEASUREMENT 

In the United States, the most commonly used precision 
temperature sensor is the thermocouple. Depending on the 
type, wire size, and construction, thermocouples can be used 
to measure temperatures from about -250°C up to 1700°C. 

When designing thermocouple-based measurement systems, 
it is helpful to understand how thermocouples work. A 
common misconception is that temperature somehow cre- 
ates an EMF in the thermocouple junction. 

Thermocouples are based on the Thomson effect, which 
states that, in a single conductor, a voltage difference will 
exist between two points that are at different temperatures. 
The voltage difference is proportional to the temperature 
differential, and its magnitude and direction depends on the 
conductor material. 

A thermocouple is formed when a pair of dissimilar conduc- 
tors are connected at one end. If a temperature difference 



exists along the length, between the two ends of the thermo- 
couple, a voltage output proportional to the temperature 
difference is generated. This phenomenon is known as the 
Seebeck effect. The measure of the Seebeck effect is known 
as the Seebeck coefficient. Seebeck coefficients for common 
thermocouple types range from about 6u.V/°C to 60(xV/°C. 

A thermocouple responds to the temperature difference 
between its output and the temperature measuring point 
where the thermocouple wires are joined. To determine the 
temperature at the measuring point you must know the 
temperature at the thermocouple output. One way to do this 
is to keep the output in an ice bath at 0°C. Thermocouple 
calibration tables were derived this way, and, following 
tradition, the thermocouple output junctions have come to be 
known as the cold junction. In reality, the measurement 
junction may be colder. 

In most modern thermocouple-based temperature measure- 
ment systems, the thermocouple output end simply resides at 
the ambient temperature. To compensate for variations in 
ambient temperature, a temperature-dependent voltage is 
summed with the thermocouple output. This method is 
known as cold-junction compensation. 

A thermocouple-based 4-20mA temperature measurement 
system with cold-junction compensation is shown in Figure 
5. In this application, a type J thermocouple is combined 
with an XTR101 to give a 4-20mA output for a 0-1000°C 
temperature change. One of the 1mA current sources in the 
XTR101 biases a silicon diode used as a temperature trans- 
ducer for cold-junction compensation. For good accuracy, 
the thermocouple output junctions and the diode must be 
maintained at the same temperature. The diode has a for- 
ward-voltage temperature dependance of about -2mV/°C. 
The R,, R 2 resistor divider attenuates the temperature depen- 



93 



dence to match the thermocouple Seebeck coefficient. The 
other 1mA current source is connected to R 3 for zero 
adjustment. The 2.5kQ resistor establishes a 5V bias to keep 
the XTR101 IA in its linear range. Adjust R 3 for 4mA out 
with the thermocouple measurement end at 0°C. The span- 
setting resistor is chosen to give a 4-20mA output for the 
58mV/1000°C thermocouple output. Nominal component 
values and Seebeck coefficients for recommended thermo- 
couples are shown in the table in Figure 5 below. 

RTD-BASED TEMPERATURE MEASUREMENT 

The highest performance temperature measurement trans- 
ducer in common use is the platinum resistance temperature 
detector (RTD). RTDs can be used to accurately measure 
temperatures from -200°C to 850°C. As with other tempera- 
ture transducers, best performance requires correction for 
nonlinearities. The XTR103 is a special purpose 4-20mA 
current-loop transmitter with built-in circuitry for RTD lin- 
earization. 

To understand how the linearization circuitry works, con- 
sider how an RTD works. In the range from 0°C to 850°C, 
the temperature/resistance relationship of a Pt-type RTD is: 

RTD = Rq • (1 + A • T + B • T 2 ) 

Where: 

RTD = DC resistance value of RTD (Q) 

at temperature T (°C) 
R = Value of RTD at 0°C (Q) 



> 















































Moal — * 


~S \ Crmr 






































— Actual 















































































200 400 600 800 1000 

Temperature (°C) 



FIGURE 6. RTD Output Voltage vs Temperature. 

Ro = 100Q for PtlOO = 200Q for Pt200 

A = Detector constant = 3.908 x 10" 3 ( C-') (for PtlOO) 

B = Detector constant = -5.802 x 10~ 7 CC" 2 ) (for PtlOO) 

The second-order term, B • T 2 , in the temperature/resistance 
relationship causes a nonlinearity in the response of =3.6% 
for a 0°C to 850°C temperature change. Figure 6 shows a 
plot of the voltage across an RTD with constant current 
excitation. The nonlinearity is exaggerated to show its char- 
acteristic shape. Increasing the current through the RTD by 
an appropriate amount as temperature increases will 
"straighten out" the curve and reduce the nonlinearity. 




4-20mA Out 



0.01 uF 

NOTE: (1 ) For 4-20mA with 0-1 000°C, R s = 1 53.912, nominal R 3 = 1 6.3£J. 



ISA THERMO- 
COUPLE TYPE 


MATERIAL 


SEEBECK 
COEFFICIENT 

AT0°C(nV/°C) 


Ri 

("> 


R 2 

(") 


R 3 

(") 


E 


Chromel 
Constantan 


58.5 


2k 


60.3 


19.0 


J 


Iron 


50.2 


2k 


51.5 


16.3 


K 


Chromel 
Alumel 


39.4 


2k 


40.2 


12.8 


T 


Copper 
Constantan 


38.0 


2k 


38.7 


12.3 





FIGURE 5. Thermocouple-Based Two- wire Temperature Measurement Using XTR101. 



RTD 
Pt100 



12 



13 



cr Si- 




:109.7a 



XTR103 



0.8-1 mA 



0.8-1 mA 




^CM 

i.27kn 



0.01 uF 



10 



11 




v+ 



4-20mA Out 



NOTE: 

^span> ^LiNt and Rz for 4-20rnA out with 
PHOO-type RTD and 25°C to 150°C temperature 
span (see PDS-1065). 



FIGURE 7. RTD-Based Two-wire Temperature Measurement Using XTR103. 



An RTD measurement circuit using the XTR103 is shown in 
Figure 7. The XTR103 is similar to the XTR101, but 
contains two instrumentation amplifiers — one in the main 
current control loop, one for linearization. 

As with the thermistor-based system, a bridge is formed with 
an RTD and a fixed resistor, R z . The bridge is excited by the 
two current sources in the XTR103. R z is selected to set the 
temperature-range zero for 4mA current loop output. The 
span-setting resistor, R SPAN , sets the IA gain for a 20mA 
current-loop output at full-scale. The 1.27kQ resistor biases 
the IA into its linear range. 

The two instrumentation amplifiers are internally connected 
in parallel. The second IA controls the current sources used 
to excite the RTD bridge. Gain of the second IA is set by 
Run- Witn Rlin °P en tne current sources are fixed at 0.8mA. 
Under control of the second IA, current source output can be 
increased to 1.0mA — adequate for-200°C to 850°C linear- 
ization of both PtlOO and Pt200 type RTDs. Current source 
output is controlled by the IA input signal according to the 
following equation. 

I REF = 0.0008 + V IN /(2 • R^) 

Where: 

I REF - Current source output (A) 

V IN = Voltage difference at the input of the IAs (V) 

With the proper R LI n> current source output is increased at 
the correct rate to correct RTD nonlinearity. Simple selec- 
tion procedures for R LIN are outlined in the XTR product 
data sheet. Request PDS-1065. 



Figure 8 shows the residual nonlinearity for a to 850°C 
span of both a linearized and an uncorrected RTD. The 
nonlinearity is improved from 3.6% to better than 0.1%, an 
improvement of better than 30 to 1. Correction of nonlinearity 
for smaller spans is even better. The nonlinearity of a 0°C to 
100°C span can theoretically be improved from 0.38% to 
0.001%. In practice, nonlinearity of better than 0.01% can be 
expected. 





4 




3.5 




3 




2.5 


t 


2 


re 




g. 


1.5 


~E. 






1 




0.5 









-0.5 





































Unco 


rrecte 


1 
































































































)rrect( 


















— C 


id 

























85 170 255 340 425 510 595 680 765 850 
Temperature (°C) 



FIGURE 8. Nonlinearity vs Temperature Plot Comparing 
Residual Nonlinearity of Corrected and 
Uncorrected RTDs. 



95 



0.01 mF 



XTR104 




E = 10mV 

R UN (or 1% nonlinearity 



NOTE: R SPAN for 10mV FS Eq, R l1n for 1% bridge nonlinearity. 



10 

13 \^ \ 



11 



2N 
2222 




V+ 



4-20mA Out 



FIGURE 9. Bridge-Based Two- wire Measurement System Using XTR104. 



BRIDGE MEASUREMENT 4-20mA 
CURRENT-LOOP SYSTEMS 

Another common transducer is based on the four-resistor 
(Wheatstone) bridge. Wheatstone bridges are commonly 
used for pressure measurement. Bridges are usually intended 
to be biased with a voltage rather than a current source. By 
changing the voltage bias in response to the bridge output, 
bridge nonlinearities can be eliminated. 

The XTR104 is a two- wire 4-20mA current loop transmitter 
designed specifically for use with bridges. It is similar to the 
XTR103 in that it contains two instrumentation amplifiers — 
one for signal, one for linearization. The difference is the 
addition of a 5V shunt regulator. The shunt regulator can be 
adjusted from 4.5V to 5.5V range under control of the 
second IA. The inputs to the second IA are brought out 
separately because, unlike RTD linearization, the correction 



signal may need to be either polarity for bridge linearizaton. 
Simple selection procedures for R LIN are outlined in the 
XTR104 product data sheet. Request PDS-1066. 

The complete bridge-based 4-20mA current loop transmitter 
circuit is shown in Figure 9. The XTR104 requires an 
external pass transistor as shown. Using an external pass 
device keeps power dissipation out of the XTR104 and 
improves accuracy. As an option, the XTR103 can use an 
external pass transistor. In either case, a garden variety 
bipolar transistor such as the 2N2222 shown is adequate. 

Notice that, as with the other two-wire transmitters, only 
2mA is available for bridge excitation. This means that, for 
accurate 5V regulation, bridge elements can be no less than 
2.75k£2 unless additional resistance is added in series with 
the bridge. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR - BROWN® 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



SINGLE-SUPPLY, LOW-POWER 
MEASUREMENTS OF BRIDGE NETWORKS 

By Bonnie Baker (602) 741-3980 



Bridge sensor measurements often need to be made in 
systems operating on a single 5V power supply. An OPA1013 
dual op amp along with a REF200 current source, makes an 
excellent bridge measurement system which features low 
power single-supply 5V operation and immunity to power 
supply variations. One OPA1013 dual op amp is used as a 
two-op-amp instrumentation amplifier. A second OPA1013 
is used with a REF200 to make two voltage references. One 
voltage reference is used to power the bridge, the other is 
used to offset the instrumentation amplifier. 

In Figure 1, A] and A 2 (an OPA1013 dual operational 
amplifier) along with one of the current sources from the 
REF200 establishes a 3.4V voltage reference for excitation 
of a pressure transducer bridge. Although the REF200 con- 



tains two current sources, the second current source is not 
used, which keeps power consumption low. 

A second OPA1013 (A 3 , A 4 ), connected as a two op amp 
instrumentation amplifier, amplifies the differential voltage 
output from the bridge. Gain is easily adjusted with R T . If 
1% resistors are used for R 4 -R 7 , common-mode rejection 
will be better than 80dB for gains greater than 200V/V. A 
CMR of 80dB is quite acceptable in this application. 

The instrumentation amplifier's reference connection is made 
to a 0.5V reference at the output of A 2 . This voltage sets an 
instrumentation amplifier offset so that a zero bridge output 
will result in a 0.5V instrumentation amplifier output. The 
value of the offset can be changed by adjusting R 3 . 



O V+ (4.5V to 36V) 



REF200 



| 100uA 




R 4 

-vVV^ 





'/2OPA1013 



0.5V 10k " 1% 



3.4V 




0.5V 




Bridge 
Sensor' 1 ! 



ssn 
iokn 1% 




R 6 

vw- 



V2OPA1013 10kQ1% 



1 




+ J OUT 
V2OPA1013 



NOTE: (1) Bridge sensor: SenSym part number BP101. 



FIGURE 1. Single-Supply Bridge Measurement Circuit. 

e 1991 Burr-Brown Corporation AB-033A 



Printed in U.S.A. January, 1992 



For V REF2 = 0.5V, R 3 = 5kft. 

For V REFI = 3.4V, R, = lk£2, R 2 = 5.8kil 

The required instrumentation amplifier gain can be calcu- 
lated from its input voltage and the output span. The output 
voltage equation is: 

Vout = V IN [2(1 + R/R T )] + V 0UT1 

This equation can be rewritten as: 

Vout = V, N • GAIN + V oim 

Where: V 0UX1 = V OUT for zero instrumentation amplifier 
input or for zero pressure applied to the pressure 
transducer, 

GAIN = -V OUT /-V IN = 2(1 + R/R T ) 
R = R 4 = R 5 = R 6 = R 7 

For example, a pressure sensor specified for 12.6mV full- 
scale output with 3.4V excitation voltage: 

GAIN = 238V/V 
if R = lOkQ, Rj = 85£2 



If adjustment is required: 
Adjustment Procedure 

1 . With zero-pressure applied, adjust R 3 for V OUT = 0.5V. 

2. Apply full-scale pressure to the sensor and adjust R T for 
V OUT = 3.5V. 

3. Repeat procedure if necessary. 

There is no true single-supply instrumentation amplifier on 
the market today. Although some come close, their applica- 
tions are limited because they are fixed gain. The OPA1013 
provides the best solution for this application because of its 
single supply operation and output swing range within 
15mV from ground. The REF200 requires one power supply 
and is ideal for use in single supply systems. The REF200 
provides a simple, economical way to make adjustable 
voltage references. 

The supply voltage of the bridge conditioning circuit can 
range from 4.5V to 36V without affecting the operation of 
the circuit. Because of the low quiescent current of the 
OPA1013 (350uA) and the low current requirements of the 
REF200 (lOOiiA), this is an excellent circuit for battery 
operated applications. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



By fl. Mar£ Sr/tt and Dav/d Kunst (602) 746-7445 



Diodes are frequently used as temperature sensors in a wide 
variety of moderate-precision temperature measurement 
applications. The relatively high temperature coefficient of 
about -2mV/°C is fairly linear. To make a temperature 
measurement system with a diode requires excitation, offset- 
ting, and amplification. The circuitry can be quite simple. 
This Bulletin contains a collection of circuits to address a 
variety of applications. 

THE DIODE 

Just about any silicon diode can be used as a temperature 
measurement transducer. But the Motorola MTS102 Silicon 
Temperature Sensor is a diode specifically designed and 
optimized for this function. It is intended for temperature 
sensing applications in automotive, consumer and industrial 
products where low cost and high accuracy are important. 
Packaged in a TO-92 package it features precise temperature 
accuracy of ±2°C from -40°C to +150°C. 

EXCITATION 

A current source is the best means for diode excitation. In 
some instances, resistor biasing can provide an adequate 
approximation, but power supply variations and ripple can 
cause significant errors with this approach. These problems 
are exacerbated in applications with low power supply 
voltages such as 5V single supply systems. Since the MTS 102 
is specified for 100|xA operation, the Burr-Brown REF200 
Dual 100u.A Current Source/Sink makes the perfect match. 
One current source can be used for excitation and the other 
current source can be used for offsetting. 

AMPLIFICATION 

In most instances, any precision op amp can be used for 
diode signal conditioning. Speed is usually not a concern. 
When ±15V supplies are available, the low cost precision 
OPA177 is recommended. For 5V single-supply applica- 
tions, the OPA1013 Dual Single-Supply op amp is recom- 
mended. Its inputs can common-mode to its negative power 
supply rail (ground in single-supply applications), and its 
output can swing to within about 15mV of the negative rail. 

Figure 1 shows the simplest diode-based temperature mea- 
surement system. One of the lOOuA current sources in the 
REF200 is used for diode excitation. The other current 
source is used for offsetting. One disadvantage of this circuit 
is that the span (GAIN) and zero (OFFSET) adjustments are 
interactive. You must either accept the initial errors or use an 



O 4.5V to 36V 




R, and R 2 are interactive. 



Figure 1. Simple Diode-based Temperature Measurement 
Circuit. 

interactive adjustment technique. Another possible disad- 
vantage is that the temperature to voltage conversion is 
inverting. In other words, a positive change in temperature 
results in a negative change in output voltage. If the output 
is to be processed in a digital system, neither of these 
limitations may be a disadvantage. 

The following relationships can be used to calculate nominal 
resistor values for the Figure 1 circuit. 

BASIC TRANSFER FUNCTION 
V o= V be(1 + IW - HXHiA • R, 

CALCULATING RESISTOR VALUES 

R , = (SyST) - (V BE25 + T c * (T M1N -25°Q) - (T c * VI) 

R 2 =R,»( (8 y r) -i) 

Where: 

R,, R 2 = Resistor values (£2) 
V BE = Voltage across diode (V) 
V be25 = Diode voltage at 25°C (V) 

Three choices are available for the MTS 102 — See table 
on page 2. 



°1991 Burr-Brown Corporation 



AB-036 



Printed in U.S.A. September, 1991 



» ! — uuij/ui vuiiagv ui buVtitt ai * MIN V v .) 

V Q = Output voltage of circuit (V) 

T c = Diode temperature coefficient (V/°C) 

T c value depends on V BE25 — See table below. 

T MIN = Minimum process temperature (°C) 

SVJST = Desired output voltage change for given 
temperature change (V/°C) 
(Note: Must be negative for Figure 1 circuit.) 

AVAILABLE VBE^ AND T c VALUES FOR 
MOTOROLA MTS102 TEMPERATURE SENSOR 



v BEB 




(V) 


(V/°C) 


0.580 


-0.002315 


0.595 


-0.002265 


0.620 


-0.002183 



EXAMPLE 

Design a temperature measurement system with a to -1 .0V 
output for a to 100°C temperature. 

T M1N = 0°C 

5VJ5T = (-1 V - 0V)/(100°C - 0°C) = -0.01V/°C 

If V BE25 = 0.595V, T c = -0.002265V/°C, and 
R = 8.424kQ 
R = 28.77k£2 

For a to -10V output with a to 100°C temperature: 
R = 6.667kQ 
R 2 = 287.7kQ 

If independent adjustment of offset and span is required 
consider the circuit shown in Figure 2. In this circuit, a third 
resistor, R ZER0 is added in series with the temperature- 
sensing diode. System zero (offset) can be adjusted with 
R ZER0 without affecting span (gain). To trim the circuit adjust 
span first. Either R, or R, (or both) can be used to adjust 
span. As with the Figure 1 circuit this circuit has the possible 
disadvantage that the temperature to voltage conversion is 
inverting. 

The following relationships can be used to calculate nominal 
resistor values for the Figure 2 circuit. 

BASIC TRANSFER FUNCTION 

V G = (V BE + lOOuA • R ZER0 ) • (1 + R/R,) - lOOuA • R, 

CALCULATING RESISTOR VALUES 

Set R ZER0 = lkQ (or use a 2kQ pot) 



R 2 = R,.(^ -1) 

Where: 

R ZER0 = Zero (offset) adjust resistor (Q) 
Others = as before 

EXAMPLE 

Design a temperature measurement system with a to -1 .0V 
output for a to 100°C temperature. 

T MW = 0°C 

8VJ8T = (-1V - 0V)/(100°C - 0°C) = -0.01V/°C 

If V BE25 = 0.595V, T c = -0.002265V/°C, and 
R ZERO = lk£2 (use 2k£2 pot) 
R,= 9.717kQ 
R 2 = 33.18kQ 

For a to -10V output with a to 100°C temperature: 
R^o = lkfl (use 2kn pot) 
R, = 7.69kH 
R 2 = 331.8kn 



O4.5Vt0 36V 



|100^A| 100pA| 



Motorola 
MTS102 





V - (V BE+ 100mA • R^) • (1 ♦ R^R,) - 100nA ■ R 2 
Where: 

V BE = voltage across diode (V) 

Adjust span first with R, or R 2 then adjust zero with R^ 
for noninteractive trim. 



(SyST) . (V BEa + (R^ . lOOuA) + T c . (T MW - 25°C» - (T c » V,) 
lOOuA.USV^-D-T,.) 



Figure 2. Diode-based Temperature Measurement Circuit 
with Independent Span (gain) and Zero (offset) 
Adjustment. 



101 



For a noninverting temperature to voltage conversion, con- 
sider the circuit shown in Figure 3. This circuit is basically 
the same as the Figure 2 circuit except that the amplifier is 
connected to the low side of the diode. With this connection, 
the temperature to voltage conversion is noninverting. As 
before, if adjustment is required, adjust span with R { or R ? 
first, then adjust zero with R ZER0 . 

A disadvantage of the Figure 3 circuit is that it requires a 
negative power supply. 

The following relationships can be used to calculate nominal 
resistor values for the Figure 3 circuit. 

BASIC TRANSFER FUNCTION 

V C= (- V BE- 100 ^ A * R ZER0 ) * (1 + W + "»JlA • R 2 

CALCULATING RESISTOR VALUES 

R, = same as Figure 2 
R, = same as Figure 2 

Where: 

Components = as before 
EXAMPLE 

Design a temperature measurement system with a to 1.0V 
output for a to 100°C temperature. 

T = 0°C 

= (IV - 0V)/(100°C - 0°C) = 0.01V/°C 
If V be25= 0.595V, T c = -0.002265V/°C, and 

R ZERO = lki2 

R, = 9.717kQ 
R 2 = 33.18kQ 

For a to 10V output with a to 100°C temperature: 

R ZERO = 

R, = 7.69kQ 
R,= 331.8k£i 




Motorola 
MTS102 



| 100M A 100mA 



6-v s 

V o = (- V BE - 1 00uA ' R ze TO ) • < 1 + R /R,) + 100MA • R 2 
Where: 

= voltage across diode (V) 

Adjust span first with R, or R 2 then adjust zero with R^ 
for noninteractive trim. 



Figure 3. Positive Transfer Function Temperature Measure- 
ment Circuit with Independent Span (gain) and 
Zero (offset) Adjustment. 

BASIC TRANSFER FUNCTION 

V D = lOO^A • R ZER0 . (1 + R^,) - V BE . IL/R, 

CALCULATING RESISTOR VALUES 

_ (T c • V,) - (SVJ8T) • (V BE2J + T c • (T MIN - 25°C)) 



R 



ZERO 



lOO^A • (T c - (SV^T)) 



R, = lOkQ (arbitrary) 

(SV^T) 
R 2 = -V(^— ) 

Where: 

Components = as before 



For a single-supply noninverting temperature to voltage 
conversion, consider the Figure 4 circuit. This circuit is 
similar to the Figure 2 circuit, except that the temperature- 
sensing diode is connected to the inverting input of the 
amplifier and the offsetting network is connected to the 
noninverting input. To prevent sensor loading, a second 
amplifier is connected as a buffer between the temp sensor 
and the amplifier. If adjustment is required, adjust span with 
R, or R 2 first, then adjust zero with R ZER0 . 

The following relationships can be used to calculate nominal 
resistor values for the Figure 4 circuit. 



EXAMPLE 

Design a temperature measurement system with a to 1 .0V 
output for a to 100°C temperature. 



T = 0°C 
'min u ^ 



= (IV - 0V)/(100°C - 0°C) = 0.01V/°C 

If V BE25 = 0.595V, T c = -0.002265V/°C, and 

R zero = 5 - 313k " 
R = lO.OkQ 

R,= 44.15k£2 



For a to 10V output with a to 100°C temperature: 

R ZER o = 6-372kQ 
R,= lO.OkQ 
R 2 =441.5kQ 



O4.5Vt0 36V 



\ (tru 

|l00uA| 100uA| 





V Q = 100uA • R Z6RO - (1 + R/R,) - V BE - R^R, 
Where: 

V BE = voltage across diode [V] 

Adjust span first with R, or R 2 then adjust zero 



Figure 4. Single-supply Positive Transfer Function Tempera- 
ture Measurement Circuit with Independent Span 
(gain) and Zero (offset) Adjustment. 

For differential temperature measurement, use the circuit 
shown in Figure 5. In this circuit, the differential output 
between two temperature sensing diodes is amplified by a 
two-op-amp instrumentation amplifier (IA). The LA is formed 
from the two op amps in a dual OPA1013 and resistors R,, 
R r R 3 , R 4 , and R SPAN . R SPAN sets the gain of the IA. For good 
common-mode rejection, R , R 2 , R 3 , and R 4 must be matched. 
If 1% resistors are used, CMR will be greater than 70dB for 
gains over 50V fV. Span and zero can be adjusted in any 
order in this circuit. 



The following relationships can be used to calculate nominal 
resistor values for the Figure 5 circuit. 

BASIC TRANSFER FUNCTION 

V D = ((V BE2 + lOOuA • R^) - (V BE1 + lOOuA • R^,)) • GAIN 
Where: 

GAIN = 2 + 2 • R,/R SPAN 

CALCULATING RESISTOR VALUES 
-2.R,.T C 



(8VJ8T) + 2 • T c 



R ZER 01 = RzERC* = 500fi ( USe lk " P 0t f0f R ZE RO ) 



Where: 
R = 

SPAN 

Others = as before 



R span = SP an (gain) adjust resistor [CI] 



EXAMPLE 

Design a temperature measurement system with a to 1.0V 
output for a to 1°C temperature differential. 

SVJ8T = (IV - 0V)/(1°C - 0°C) = 1.0V/°C 
If V BE25 = 0.595V, T c = -0.002265V/°C, and 

R ZERO = lkfl P 0t 

R,, R 2 , R 3 , R 4 = lOOkQ, 1% 
r SPA n = 455ft 

For a to 10V output with a to 1°C temperature differen- 
tial: 

R ZERO = lk£2 P 0t 

R,, Rj, R 3 , R 4 = lOOkQ, 1% 
R span = 45.3Q 



O 4.5V to 36V 




Figure 5. Differential Temperature Measurement Circuit. 




"APPLICATION BULLETIN 



Burr-Brown Corporation • 



PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



105 



SINGLE-SUPPLY OPERATION OF ISOLATION AMPLIFIERS 

By Rod Burt and R. Mark Stitt (602) 746-7445 



For simplicity, many systems are designed to operate from a 
single external power supply. In battery powered systems 
such as aircraft and automotive, it's often a requirement. 
Isolation amplifiers such as the ISO 120 and ISO 122 can be 
easily modified for input side single-supply operation with 
the addition of an INA105 difference amplifier. With ISO 
amps, it's the isolated input side power supply which most 
often needs to be single supply. The output side of the ISO 
amp uses a split +15V power supply, allowing a full +10V 
output swing. 

The difference amplifier has advantages as compared to 
traditional single-supply amplifiers. The inputs of a differ- 
ence amplifier can swing to both the positive and negative 
power-supply rails. In fact, in the application shown in 
Figures 1 and 2, the input range of the circuit extends 
approximately 2V below ground (the negative power supply 
rail). This is because the resistors internal to the INA105 
divide the input level in half as seen by the op amp. 

The technique is illustrated in Figures 1 and 2 using the 
ISO 120 and ISO 122. These ISO amps are specified for 
operation from dual supplies as low as ±4.5V and can be 
operated with a total single power supply voltage as low as 
9 V. The circuit shown is designed for operation from a single 
+15V power supply. This allows a 0V to +5V input range. 



The most common application is for a single ended input 
referred to ground as shown. For a differential input, pin 2 
can be connected to a second input instead of ground. This 
provides a 0V to 5 V differential input with common-mode to 
either rail. 

To understand how the circuit works, consider the operation 
of the INA105 difference amplifier. The difference amplifier 
forces its output (pin 6) relative to its reference (pin 1) to be 
equal to the differential input (pin 3 - pin 2). The difference 
amplifier reference pin and the ISO amp common are held at 
approximately 5.1V by the 10k£2 resistor and the zener 
diode. This pseudo ground establishes an arbitrary accept- 
able operating point for the ISO amp. The difference ampli- 
fier then translates its input, relative to true ground, up to the 
5.1V pseudo ground. In other words, a 0V to 5V input 
between pins 3 and 2 of the INA105 is seen as a 0V to 5V 
signal at the ISO amp input. 

Isolated power is often at a premium and both the ISO 120/ 
1 22 and the INA 1 05 operate on relatively low power. Common 
zener diodes, on the other hand, may require several mA for 
proper operation. The 1N4689 zener diode specified is a low 
level type designed for applications requiring low operating 
currents. It has a sharp breakdown voltage specified at a low 
50uA. 



Signal Source 




V S1 (+15V)0 



INA105 
Difference Amp 



NOTE: (1) Select to match R s . 



O+Vgj (+15V) 




1 Votrr = V. 



r> 

1 

E 



o 

g 

Q. 

a 
< 



FIGURE 1. Single Supply Operation of the ISO 122 Isolation Amplifier. 



<8 1990 Burr-Brown Corporation 





AB-009A 



Printed in U.S.A. August. 1991 



- 



V S1 (+15V) o 



1 



Signal Source 




INA105 
Difference Amp 



R, 




5 10 k£j- 



IN4689 
5.1V 



NOTE: (1) Select to match R s . 



23 



22 



21 



24 



O +V S2 (+15V) 



In 

ISO 
120 

Osc 

Com 
Gnd 



Hi 



16 



VqUT - V|N 



VCom2 
6 -V S2 (-15V) 



FIGURE 2. Single Supply Operation of the ISO 120 Isolation Amplifier. 



The accuracy of the INA105 difference amplifier relies on 
careful resistor ratio matching (R 3 /R, = R,/R 2 ). Any source 
impedance of the signal (R s ) adds to the difference resistor 
(R 3 ). For low source impedances, the error is acceptable. For 
better accuracy at higher source impedances, a compensating 
resistor (R c ) can be added to restore the ratio matching. The 
resistors in the INA105 are 25kQ. For 0.1% gain accuracy, 
no compensating resistor is required with source impedances 
up to 25Q. For source impedances up to 2.5kQ, use a 
compensating resistor which matches R s within 1%. If the 
source impedance is not known exactly, a trim pot can be 
used to adjust gain accuracy. 

For operation with source impedances greater than 2.5k£2, a 
unity-gain-connected single-supply op amp can be added to 
buffer the input as shown in Figure 3. Although the input 



range of the OPA1013 single-supply op amp includes the 
negative rail, its output can not quite swing all the way to the 
rail. The negative swing limit of this circuit is therefore 
= 100mV — still adequate in many applications. 

For an instrumentation amplifier (IA) front end, the other 
half of the OPA1013 can be connected to the inverting input 
of the INA105 (pin 2) as shown in Figure 4. 

For a true single-supply ISO amp with high impedance 
differential inputs, the circuit shown in Figure 5 can be used. 
In this circuit, the inputs — and therefore the outputs — of the 
OPA1013s are level-shifted up a V BE with a matched pair of 
PNP input transistors. The transistors are biased as emitter 
followers by a pair of lOOuA current sources contained in the 
REF200 dual current source. 



V S1 (+15V) o 



I 




INA105 
Difference Amp 



R, 



R 3 




10k£2- 



Reference 



IN4689 ' 
5.1V 



15 



16 



9+Vgj (+15V) 



ISO 
122 

Gnd 




10 



Vout = V, N 



V 



Com 2 



6 -V^ (-15V) 



FIGURE 3. Single Supply (almost — see text), High Input Impedance Isolation Amplifier. 



107 



The circuits shown in this bulletin were designed for OV to 
5V operation from a single +15V power supply. With re- 
duced range, operation from a lower voltage is feasible. For 
higher input range the circuit can be operated from a higher 
supply voltage. Table 1 shows the ranges obtainable for 
selected power supplies. 



(V) 


INPUT RANGE 
FIGURES 1, 2 

(V)"' 


INPUT RANGE 
FIGURES 3, 4 

(V)»> 


INPUT RANGE 
FIGURE 5 

( V)«> 


20+ 


-2 to +10 


0.1 to +10 


-0.3 to +10 


15 


-2 to +5 


0.1 to +5 


-0.3 to +5 


12 


-2 to +2 


0.1 to +2 


-0.3 to +2 


Note: (1 ) Since the amplifier is unity gain, the input range is also the output 
range. The output can go to -2V since the output section of the ISO amp 
operates from dual supplies. 



TABLE 1 . Single-Supply ISO Amp Input Range vs Power 
Supply. 



V s , (+15V) O 





INA105 
Difference Amp 



R 3 

-m- 



R 2 




R 4 



5 lOkiT 



Reference - 



IN4689 
5.1V 



15 



16 



O+Vgj (+15V) 



ISO 

122 

Gnd 



10 



2 

-V* 



V UT=Vp-V N 



\7com2 
6 -Vk (-15V) 



FIGURE 4. Single Supply (almost — see text), Isolation Amplifier with High-Impedance Differential Inputs.. 



V S1 (+15V)0 



Q) 100uA (J) 
REF200 



VpO- 



MAT03 





INA105 
Difference Amp 



R 2 



-vw- 




R4 



iokn- 



Reference - 



IN4689 ' 
5.1V 



15 



16 



O+V^ (+15V) 



ISO 
122 

Gnd. 



^S^VouT-Vp-V 



10 



VCom2 
6 -Vs, (-15V) 



FIGURE 5. Single Supply Isolation Amplifier with High-] 



Differential Inputs. 



voltage differential inputs, an INA117 high common-mode 
voltage difference amplifier can be substituted for the INA 1 05 
difference amplifier as shown in Figure 6. With a +15V 



mately +125V, -50V. With a +12V supply, the input com- 
mon mode range is approximately +50V. Differential input 
range remains as shown in Table I for Figures 1 and 2. 



V s , (+15V) Q 



v 3 0— 



-vW- 



380kQ 



380kl! 



380kn 




21.1kn- 



-20kn 



8 1 5 



INA117 



iokn- 



Reference 



IN4689 ' 
5.1V 



O +V S2 (+15V) 



ISO 
120 

Com 
Gnd 

4 




10 



16 



Vout=V 3 -V 2 



12 



VCom2 
6 -Vsz (-15V) 



FIGURE 6. Single Supply Isolation Amplifier with High Common-Mode Range Differential Inputs. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR - BROWN 




APPLICATION BULLETIN 



Burr-Brown Corporation • 



PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



BOOST ISO120 BANDWIDTH TO MORE THAN 100kHz 

By R. Mark Stitt and Rod Burt (602) 746-7445 



There has been considerable demand for high-bandwidth 
isolation amplifiers. The highest bandwidth Burr-Brown 
ISO amps are the ISO100 and the ISO120/121/122 family 
with bandwidths of about 50kHz. The ISO 120/1 21 bandwidth 
can be boosted to more than 100kHz by adding gain in the 
feedback. 

Adding gain in the feedback of the ISO 120/1 21 increases 
bandwidth and decreases phase margin — see Figure 4. The 
ISO 120 was designed with approximately 70° phase margin 
in the output stage for maximally flat magnitude response 
and a f_ MB bandwidth of approximately 50kHz. With a gain 
of 2.4 V/V in the feedback as shown in Figure 1, phase 
margin is decreased to an acceptable 45°. Due to gain 
peaking, the actual f MB bandwidth is increased to almost 
150kHz. With the addition of an input filter as shown in 
Figure 2, flat magnitude response with a bandwidth of 



greater than 100kHz is obtained. Since the added gain is 
within the ISO 120 feedback loop, the overall gain of the 
isolation amplifier is unchanged (gain = 1). 

To verify the phase margin, analyze the step response of the 
Figure 1 circuit (shown in the Scope Photo 1). The 25% 
overshoot translates to a damping factor of 0.4 and 45° phase 
margin. 

If the ISO 120 is used in the clocked mode, maximum 
bandwidth is determined by the clock frequency. For 150kHz 
bandwidth and 45° phase margin with a gain of 2.4V/V in 
the ISO 120 feedback, the clock frequency should be 500kHz. 
Lower clock frequencies will result in reduced phase margin 
and possible instability. Higher clock frequencies will result 
in better phase margin, but clock frequencies above 700kHz 
are not recommended. 



+4.5Vto+18VO 



4.5V to -18V 6 




Vour-V w 




Step response of Figure 1 circuit showing 25% overshoot 
which translates into 45° phase-margin. 



FIGURE 1. ISO 120 with f Bandwidth Boosted to Approximately 150kHz. 



+4.5Vto+18VO 



v IN o^v\A- 



l.5Vto-18V 6 



-O +15V 




-O -15V 



response of Figure 2 circuit. 



FIGURE 2. ISO 120 with Flat Magnitude Response and f Bandwidth Boosted to More Than 100kHz. 



°1990 Burr-Brown Corporation 



AB-012A 



Printed in U.S.A. September. 1990 



Adding gain in the feedback of the ISO120 can also increase 
its slew rate and full-power response. So long as the op amp 
providing gain in the feedback has adequate slew rate, the 
2V/(j.s slew rate of the ISO 120 is multiplied by its gain. 
When using an OPA602 with a gain of 2.4V/V in the 
feedback, the 30kHz 20Vp-p full-power response of the 
ISO 120 is increased to more than 70kHz. Driving the OPA602 
input below about -12V will cause signal inversion and 
possible circuit lock-up. The 470£2/back-to-back zener net- 
work prevents possible lock-up by keeping the op amp input 
from being driven beyond its linear common-mode input 
range. 

The addition of an input filter to compensate for the gain 
peaking, as shown in Figure 2, gives a flat magnitude 
response of more than 100kHz. In addition to the gain of 



2.4V/V amplifier in the feedback, a simple 80kHz input 
filter formed by C, and R, is inserted at the input. The lOkQ 
input resistor, R 3 , decreases the ISO 120 gain by about 5%. 
A matching 10k£2 resistor in the feedback, R 4 , restores gain 
accuracy. The step response for the Figure 2 circuit is shown 
in the scope photo. 

The Gain vs Frequency Plot, Figure 3, compares the 
response of the Figure 1 and Figure 2 circuits, to the standard 
ISO 120. The top plot is the Figure 1 circuit showing about 
+3dB magnitude peaking and almost 150kHz f MB bandwidth. 
The center plot is the Figure 2 circuit with the 80kHz input 
filter. The magnitude response is flat with an f MB bandwidth 
greater than 100kHz. The bottom plot shows the standard 
ISO 120 circuit with an f bandwidth of about 50kHz. 




Gain vs Frequency plot comparing: 1) Figure 1 circuit showing almost 150kHz f^ B bandwidth with +3dB gain peaking, 2) Figure 2 circuit showing flat 
magnitude response and more than 100kHz f^, B bandwidth, and 3) standard ISO120 showing 50kHz bandwidth. 



FIGURE 3. Gain vs Frequency Plot. 



Ill 



From — 
Input 
Section 1 PF 




'-3dB ~ 275kHz Bucket-Brigade 
Low-Pass Sample/Hold 



G = 2.4V/V 
or 

Short (G = 1) 

The output demodulator section of the ISO120/121/122 consists of the integrator loop shown. This technique can not be applied to the IS0122 because 
the feedback connection is not available externally. Stability is determined by the phase margin at the open-loop response unity gain point, f UQ . 

The unity-gain frequency is: 

6.28 • gain._. 
— -. 33kHz • gain EXT 



f,. 



The phase margin is approximated by: 



180° - 



90° 



2«>t(200ka)-(150pF) 

tan-' (f^SkHz) 



1us • f u 



■ 360° 



200kn, 150pF higher order 

integrator poles 

"The sample/hold delay is 1/(2 • freq CLK ). For a 500kHz clock frequency, the delay is 1us. The free-running clock frequency is approximately 500kHz. 

Forgain s _-l: 



■■ 33kHz, Phase Margin = 70", and 



For gain EXT = 2.4: 

f U8 = 80kHz, phase margin = 45°, and 

f^,,, = 150kHz with +3dB gain peaking at 80kHz. 



FIGURE 4. Analysis of ISO 120/1 21 Demodulator Section. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



By Rod Burt and R. Mark Stitt (602) 746-7445 



Internal clock circuitry in the ISO120/121 precision isola- 
tion amplifier (ISO amp) can be synchronized to an external 
clock signal. Synchronization to an external clock can be 
used to eliminate beat frequencies in multichannel systems 
or for rejection of specific AC signals and their harmonics — 
see the ISO 120/1 21 product data sheet, PDS-820. 

The external clock signal can be directly connected to the 
ISO 120/1 21 if it is a sine or triangle wave of the proper 
amplitude. At clock frequencies above 400kHz, a square 
wave external clock can also be directly connected to the 
ISOl 20/121. Other clock signals can be used with the 
addition of the signal conditioning circuit shown in Figure 2. 

SYNCHRONIZING TO A SINE 

OR TRIANGLE WAVE EXTERNAL CLOCK 

The ideal external clock signal for the ISO120/121 is a +4V 
sine wave or +4V, 50% duty-cycle triangle wave. The ext osc 
pin of the ISO120/121 can be driven directly with a +3V to 
±5V sine or 25% to 75% duty-cycle triangle wave and the 
ISO amp's internal modulator/demodulator circuitry will 
synchronize to the signal. 



EXTERNAL CLOCK 
FREQUENCY RANGE 


C,,C l ISO120n21 
MODULATOR, DEMODULATOR 
EXTERNAL CAPACITOR 


400kHz to 700kHz 
200kHz to 400kHz 
100kHz to 200kHz 
50kHz to 100kHz 
20kHz to 50kHz 
10kHz to 20kHz 
5kHz to 10kHz 


none 
500pF 
1000pF 
2200pF 
4700pF 
0.01 uF 
0.022uF 



TABLE L Recommended ISO 120/1 21 External Modulator/ 
Demodulator Capacitor Values vs External Clock 
Frequency. 



EXTERNAL CLOCK 


c, 


400kHz to 700kHz 


30pF 


200kHz to 400kHz 


180pF 


100kHz to 200kHz 


680pF 


50kHz to 100kHz 


1800pF 


20kHz to 50kHz 


3300pF 


10kHz to 20kHz 


0.01 uF 


5kHz to 10kHz 


0.022uF 



TABLE II. Recommended C x 
Figure 2 Circuit. 



Values vs Frequency for 



Optional External 
Modulator 



I 



Ext 
Osc 



200kfi 

-vV\A- 




Optional External 
Demodulator 
Capacitor 



C ° 2 



150pF 







Bucket- 






Brigade 




Sample/ 




Hold 



200k£J 



G = 2rt 



ISO120/121 

Demodulator 



V 
-O 



FIGURE 1. ISO 120/1 21 Block Diagram Showing Internal Clamp and Filter Circuitry at the Ext Osc Pin. 

e l991 Burr-Brown Corporation AB-021 Printed in U.S.A. January, 1991 



Synchronizing to signals below 400kHz requires the addi- 
tion of two external capacitors to the ISO 120/121. Connect 
one capacitor in parallel with the internal modulator capacitor 
and connect the other capacitor in parallel with the internal 
demodulator capacitor as shown in Figure 1. 

The value of the external modulator capacitor, C,, depends 
on the frequency of the external clock signal. Table I lists 
recommended values. 

The value of the external demodulator capacitor, C 2 , de- 
pends on the value of the external modulator capacitor. To 
assure stability, C, must be greater than 0.8 • C,. A larger 
value for C, will decrease bandwidth and improve stability: 
f 1-2 
3dB 200kQ(150pF + C 2 ) 

Where: 

f = -3dB bandwidth of ISO amp with external C, (Hz) 
C 2 = External demodulator capacitor (F) 

For example, with C 2 = 0.0 luF, the f_ MB bandwidth of the 
ISO 120/1 21 is approximately 600Hz. 

SYNCHRONIZING TO A 400kHz TO 700kHz 
SQUARE-WAVE EXTERNAL CLOCK 

At frequencies above 400kHz, an internal clamp and filter 
provides signal conditioning so that a square-wave signal 
can be used to directly drive the ISO 120/1 21. A square-wave 
external clock signal can be used to directly drive the 
ISO 120/1 21 ext osc pin if: the signal is in the 400kHz to 
700kHz frequency range with a 25% to 75% duty cycle, and 
±3V to +20V level. Details of the internal clamp and filter 
circuitry are shown in Figure L 



SYNCHRONIZING TO A 10% TO 90% 
DUTY-CYCLE EXTERNAL CLOCK 

With the addition of the signal conditioning circuit shown in 
Figure 2, any 10% to 90% duty-cycle square- wave signal 
can be used to drive the ISO 120/1 21 ext osc pin. With the 
values shown, the circuit can be driven by a 4Vp-p TTL 
signal. For a higher or lower voltage input, increase or 
decrease the lkQ resistor, R x , proportionally, e.g. for a ±4V 
square wave (8Vp-p) R x should be increased to 2k£2. 

The value of C x used in the Figure 2 circuit depends on the 
frequency of the external clock signal. Table II shows 
recommended capacitor values. 

Note: For external clock frequencies below 400kHz, exter- 
nal modulator/demodulator capacitors are required on the 
ISO 120/1 21 as before. 



1uF R x 

° II Uh 

Sq Wave In h<q 



10kfi 




Triangle Out 
to ISO120/121 
Ext Osc 



FIGURE 2. Square Wave to Triangle Wave Signal Condi- 
tioner for Driving ISO120/121 Ext Osc Pin. 



BURR - BROWN 




"APPLICATION BULLETIN 



Burr-Brown Corporation • 



PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



SIMPLE OUTPUT FILTER ELIMINATES 
ISO AMP OUTPUT RIPPLE AND KEEPS FULL BANDWIDTH 

By Mark Stitt (602) 746-7445 



The ISO120/121/122 isolation amplifiers (ISO amps) have a 
small (10-20mVp-p typ) residual demodulator ripple at the 
output. A simple filter can be added to eliminate the output 
ripple without decreasing the 50kHz signal bandwidth of the 
ISO amp. 

The ISO 120/1 2 1/1 22 is designed to have a 50kHz single- 
pole (Butterworth) signal response. By cascading the ISO 
amp with a simple 50kHz, Q = 1, two-pole, low-pass filter, 
the overall signal response becomes three-pole Butterworth. 
The result is a maximally flat 50kHz magnitude response 
and the output ripple reduced below the noise level. 

Figure 1 shows the complete circuit. The two-pole filter is a 
unity-gain Sallen-Key type consisting of A,, R , R 2 , C r and 
C,. The values shown give Q = 1 and f bandwidth = 50kHz. 
Since the op amp is connected as a unity-gain follower, gain 
and gain accuracy of the ISO amp are unaffected. Using a 
precision op amp such as the OPA602 also preserves the DC 
accuracy of the ISO amp. 

Figure 2 compares the magnitude response of the standard 
and filtered ISO amp. Figures 3 and 4 show the output ripple 
improvement. Figures 5 and 6 show the good step response 
of both the standard and filtered ISO amp. 



+3 

-3 

S -9 

g 

'ra 

O -15 
-21 


GAIN vs FREQUENCY 




























































































































































































2 












































































































































2k 5k 10k 20k 50k 100k 200k 
Frequency (Hz) 

1) Standard IS0122 has 50kHz single-pole (Butterworth) re- 
sponse. 

2) IS0122 with cascaded 50kHz, Q = 1, two-pole, low-pass 
filter has three-pole Butterworth response. 



FIGURE 2. Gain vs Frequency Plot. 







Gnd1 



Q 



c 2 

1000pF 




4.75W1 




9.76k£2 



-ov Q 



Gnd2 



NOTE: Cascading the 50kHz single-pole response IS0122 with a 50kHz, Q = 1, two-pole, low-pass 
filter produces an overall three-pole Butterworth response and eliminates output ripple. 



FIGURE 1. ISO 122 with Output Filter for Improved Ripple. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



1991 Burr-Brown Corporation 



AB-023 



Printed in U.S.A. January, 1991 




FIGURE 3. Standard ISO 122 (approximately 20mVp-p FIGURE 4. Filtered ISO 122 (no visible output ripple), 
output ripple). 




FIGURE 5. Step Response of Standard ISO 122. FIGURE 6. Step Response of ISO 122 with Added Two- 

pole Output Filter. 




NOTE: Ripple is eliminated from the output waveform by the filter. 



FIGURE 7. Large-signal, 10kHz Sine-wave Response of 
ISO 122 with and without Output Filter. 



BURR - BROWN® 



IMM1 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: TO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



VERY LOW COST ANALOG ISOLATION WITH POWER 

By Mark Stitt (602) 746-7445 



You can make a low-cost, precision analog isolation ampli- 
fier (ISO amp) with power by combining the ISO 122 low- 
cost ISO amp with the HPR1 17 low-cost DC/DC converter. 
With isolated signal and isolated power in separate packages, 
complete application flexibility is assured. 

The IS0122 features: 

• Unity gain (±10V In to ±10V Out): ±0.05% 

• 0.02% max nonlinearity 

• 5mA quiescent current 

• 140dB isolation mode rejection at 60Hz 

• 1500Vrms continuous isolation rating (100% tested) 

The HPR117 features: 

• V 0UT = V w , +5% (V w = 13.5V to 16.5V, I OUT = 25mA) 

• I 0UT = 25mA (750m W) continuous at 85°C 

• 8mA quiescent current, no load 

• 80% efficiency, full load 

• Low output ripple 

• 750VDC isolation rating 



OUTPUT-SIDE POWERED ISO AMP 

The most commonly used ISO amp configuration is shown 
in Figure 1. Both the ISO amp and the DC/DC converter are 
powered at the output side of the ISO amp. The HPR1 17 is 
connected to +15V and ground. The ISO 122 is connected to 
±15V and ground. The power-supply connections for the 
input side of the ISO amp are connected directly to the 
HPR117 output. No bypass capacitors are needed. The 
HPR1 17 has built-in 0.33(iF bypass capacitors on both the 
input and outputs. 

The isolated ±15V power output from the HPR1 17 can also 
be used for ancillary input-side circuitry such as input 
amplifiers and references. The ISO 122 input section con- 
sumes about ±5mA. An additional ±20mA is available for 
other circuitry. 

INPUT-SIDE POWERED ISO AMP 

Some applications call for output-side isolation as shown in 
Figure 2. Isolated +15V, 20mA auxiliary power is available 
on the output side for ancillary circuitry. 



Input 
Gnd 



O +15V 



0-15V 



Auxiliary 
Isolated 
Power 
Output 

+15V,20mAO 
-15V, 20mA O 




FIGURE I. Output-Side Powered ISO Amp. 



s 1991 Burr-Brown Corporation 



AB-024 



Printed in U.S.A. March, 1991 



v,„o 




-O -15V, 20mA 



-O +15V, 20mA 



Auxiliary 
Isolated 
Power 
Output 



_q Output 
Gnd 



-15V O 



-O V n 



FIGURE 2. Input-Side Powered ISO Amp. 



+15V O Q Gnd 



v IN o- 



Input ( 
Gnd 



Auxiliary 
Isolated 
Power 
Output 

+15V, 20mA O- 



-15V, 20mA O- 



HPR117 



HPR117 

n 



04 05 06 



16 15 

I Gnd V, N 7 / 

K INPUT V V 

J SECTION ISO x 12: 



10 9 



INPUT 
SECTION 

V+ V- 



IS0122P 

)1 



V- v+ 

OUTPUT 
SECTION 

V n Gnd 



-0-15V, 20mA 



-O +15V, 20mA 

Auxiliary 
Isolated 
Power 
Output 



! Output 

' Gnd 



-O V„ 



FIGURE 3. Powered ISO Amp with Three-Port Isolation. 



THREE PORT ISO AMP 

Some applications call for three-port isolation as shown in 
Figure 3. Both the input and output side of the ISO amp are 
isolated from the power-supply connection. Isolated ±15 V, 
20mA auxiliary power is available on both the input and 
output side of the ISO amp. 



ADD RC FILTER TO POWER 
SUPPLY OUTPUT FOR LOW NOISE 

Although performance is good using the ISO 122 connected 
directly to the HPR1 17, best performance can be achieved 
with additional filtering. The output ripple of the HPR117 
can interact with the ISO 122 modulator/demodulator cir- 



119 



lOuS 



— ™ 



itiniTrnfifniniTriTiniiT 

mmiminmiimnm" 





FIGURE 4. Oscilloscope Photograph Showing Typical 
HPR117 Power Supply Ripple (bottom trace) 
and Typical 30kHz, 30mVp-p Noise at the 
ISO 122 Output Due to Aliasing of Power Sup- 
ply Ripple. 



cuitry through the power-supply pins resulting in an aliased 
noise signal within the signal bandwidth of the ISO amp. 
The 30kHz, 30mVp-p upper trace in Figure 4's scope photo 
is a typical example. The lower trace in the scope photo is 
the HPR1 17 output ripple with the ISO 122 plus a 2kQ load. 
Adding simple R, C filters in the outputs from the HPR1 17 
as shown in Figure 5 eliminates the problem. 

The R,C filter shown in Figure 5 can also be used with either 
the Figure 1 or Figure 2 circuit. Since the DC/DC converter 
can induce a substantial amount of ripple on input-side 
connections, filters may still be needed on both the input- 
side and output-side power supply connections of the ISO 122 
to prevent noise due to signal aliasing. 

The filter resistors will degrade the load regulation of the 
DC/DC converters. In addition to the specified HPR1 17 load 
regulation, there will be an additional 50mV/mA drop through 
the 50Q filter resistors. Although this results in only a 1.25 V 
drop at the full-rated 25mA output, you may want to use 
smaller value resistors and commensurately larger value 
filter capacitors if power-supply sensitive ancillary circuitry 
is needed. 



+15VO o Gnd 



6 5 4 





50£2- 



1uF 



v IN o- 



Input 
Gnd 



Auxiliary 
Isolated 
Power 
Output 

+15V, 20mA O 



u 

HPR117 

)1 



.50a 



01 02 



HPP.117 

J) 



04 05 06 



50Q- 



1uF 



-15V, 20mA °- 



16 15 



Gnd V IN 

INPUT 
SECTION 

V+ V- 



If 

IS0122P 

Jl 



1uF 



10 



V- v+ 

OUTPUT 
SECTION 

V„ Gnd 



:son 



IMF 



-O -15V, 20mA 



-O +15V, 20mA 

Auxiliary 
Isolated 
Power 
Output 



Output 
Gnd 



-ov„ 



FIGURE 5. Three-Port Isolation Amplifier with R, C Power Supply Filters (eliminates power-supply induced noise). 



6 5 4 

9 




0.01 uF 



m^-vw — ©— 

90.9kn Qn Q1 ' ri 



v, N o- 

Input 
Gnd 



HPR117 

Jl 



2 1 





0.01 uF 

Hh- 



90.9kH 



V' 2 REF200 



Auxiliary 
Isolated 
Power 
Output 

+9V, 5mA O 

-9V, 5mA O- 
NOTE: (1) 1/2 MC1458 low-cost dual op amp. 



+15V Q O Gnd 




TC 

1PR1 

Jl 



2 ^ ^ C)4 
HPR117 



V4REF200 



10 



V- v+ 



OUTPUT 
SECTION 




-O -9V, 5mA 



-O +9V, 5mA 
Auxiliary 



Output 



Output 



Grid 

-ov 



FIGURE 6. Power Supply Regulation in Three-Port Isolation Amplifier (eliminates power-supply induced noise and improves 
power-supply rejection). 



ADD REGULATION FOR IMPROVED 
POWER-SUPPLY REJECTION 

Output ripple can be eliminated and power-supply rejection 
of the three-port isolation amplifier can be improved as 
shown in Figure 6. The circuit consists of a dual lOOuA 
current source (the REF200) driving 90.9kQ resistors to set- 
up a ±9.09V reference. An inexpensive dual op amp (e.g. 
Motorola MCI 458) is connected as a unity-gain follower to 



buffer the reference and drive the ISO 122. With this circuit, 
the power-supply rejection is improved from a typical 2m V/ 
V to less than ±lmV for a full 14V to 16.5V input change — 
(0.4mV/V). 

When using the Figure 6 circuit, ISO amp output swing will 
be reduced. The IS0122 output swing is ±12.5V typ, +10V 
min on ±15V supplies. With the ±9V regulated supplies, 
output swing will be ±6.5V typ, ±4V min. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR -BROWN® 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



MAKE A PRECISION CURRENT SOURCE OR CURRENT SINK 

By R. Mark Stitt (602) 746-7445 



The introduction of the REF200 Dual Current Source has 
fostered a great deal of interest in current sources and 
current sinks. The AN- 165 application guide, Implementa- 
tion and Application of Current Sources and Current Re- 
ceivers, was intended to answer customers' questions about 
design and applications of current sources/sinks and current 
to voltage converters of all kinds (not just the REF200). 

A frequently asked question, not answered by the guide, has 
been: "How do I make the world's most accurate current 
source and current sink?" Figures 1 and 2 respectively show 
the circuits for making precision current sources and sinks. 

The precision current source and sink are based on the new 
REF102 10.0V voltage reference. With 2.5ppm/°C V OUT 
drift, and better than 5ppm/1000hrs long-term stability (see 
table on page 2), this buried-zener-based voltage reference 
offers the best performance available from a single-chip 
voltage reference today. The REF200 uses a band-gap type 
reference to allow low-voltage two-terminal operation. This 
makes it a good general-purpose part, but its drift and 
stability and initial accuracy cannot compare to that of the 
REF102. 

The current source is shown in Figure 1. The voltage- 
follower connected op amp forces the voltage reference 
ground connection to be equal to the load voltage. The 
reference output then forces an accurate 10.0V across Rj so 
that the current output is 10V/R,. 



v+ 

REF102 

+10V 
Out 



Gnd 




-10V/R, 



LOAD 



Can be connected 
to ground or -V s . 



The current sink is shown in Figure 2. The op amp drives 
both the voltage reference ground connection and the cur- 
rent-scaling resistor, so that the voltage reference output 
is equal to the load voltage. This forces -10.0V across R, so 
that the current sink output is -10V/R,. The R 2 , C, network 
provides local feedback around the op amp to assure loop 
stability. It also provides noise filtering. With the values 
shown, the reference noise is filtered by a single pole with 
t = 1/(2 • it • R • C.) = 16kHz. 




i OUT = -iovm, 



LOAD 



Can be connected 
to ground or +V S . 



FIGURE 1 . Precision Current Source. 



FIGURE 2. Precision Current Sink. 

Compliance of the circuit depends on input and output range 
of the op amp used and the 1 1.4V minimum supply range of 
the REF102. The application guide goes into more detail. 

Keep in mind that the accuracy of a voltage-reference-based 
current source depends on the absolute accuracy of the 
current scaling resistor (R,). The absolute TCR and stability 
of the resistor directly affect the current source temperature 
drift and stability. If you use a 50ppm/°C resistor (common 
for 1 % metal film resistors), the precision current source will 
have approximately 50ppm/°C drift with temperature — worse 
than the 25ppm/°C drift of a REF200. 



E 1990 Burr-Brown Corporation 



AB-002B 



Printed in U.S.A. February, 1991 



The performance of circuits using current source references 
depends only on the ratio accuracy of the scaling resistors. 
It is much easier to get good resistor ratio accuracy than to 
get good absolute accuracy, especially when using resistor 
networks. 



Burr-Brown offers a wide variety of support components 
which are excellent choices for generation or conversion of 
current. Application Guide (AN- 165) has proven valuable in 
selecting these components. 



REF102CM +10.0V REFERENCE STABILITY vs TIME 

T>25°C, V S =+15V. 



UNIT 


^out CHANGE 
FROM 1 HR 
TO 168 HRS 
[ppm] 


V 0UT CHANGE 
FROM 1 HR 
TO 1008 HRS 
[ppm] 


V 0UT CHANGE 
FROM 1 HR 
TO 2016 HRS 
[ppm] 


V 0UT CHANGE 
FROM 1 HR 
TO 3072 HRS 
[ppm] 


^our CHANGE 
FROM 1 HR 
TO 5136 HRS 
[ppm] 


V OUT CHANGE 
FROM 1 HR 
TO 14205 HRS 
[ppm] 


1 


6.8 


5.5 


7.1 


4.7 


8.2 


11.7 


2 


5.1 


1.0 


1.2 


-2.1 


0.1 


1.3 


3 


9.4 


6.5 


3.2 


1.0 


1.8 


2.0 


4 


9.6 


6.9 


7.7 


5.6 


7.6 


10.3 


5 


12.9 


7.8 


9.6 


6.7 


9.5 


12.8 


6 


10.5 


6.4 


5.3 


3.0 


5.4 


9.4 


7 


10.3 


5.7 


6.2 


3.7 


5.8 


8.2 


8 


17.0 


14.5 


12.9 


9.2 


9.9 


13.7 


9 


6.2 


5.1 


3.8 


1.7 


2.7 


4.1 


10 


7.1 


1.7 


1.3 


0.1 


1.0 


2.4 


11 


13.0 


9.6 


9.6 


10.0 


13.0 


16.5 


12 


7.5 


4.7 


3.9 


4.2 


5.0 


7.4 


13 


13.0 


9.5 


10.4 


8.2 


9.9 


13.7 


14 


4.2 


3.0 


0.5 


-0.3 


4.2 


2.8 


15 


7.3 


4.3 


2.6 


1.8 


4.1 


3.9 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR - BROWN 




APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



123 



VOLTAGE-REFERENCE FILTERS 



By R. Mark Stitt (602) 746-7445 



IMPROVED VOLTAGE-REFERENCE 
FILTER HAS SEVERAL ADVANTAGES 

• LOW OUTPUT IMPEDANCE AT HIGH 
FREQUENCY FOR DRIVING DYNAMIC LOADS 
SUCH AS HIGH-SPEED A/D CONVERTERS 

• IMPROVED NOISE FILTERING 

• BETTER ACCURACY BY ELIMINATING 
CAPACITOR LEAKAGE ERRORS 

• DRIVES LARGE CAPACITIVE LOADS 

The Burr-Brown REF102 is a buried-zener-based precision 
10.0V reference. It has better stability and about five times 
lower output noise than band-gap-based voltage references 
such as the PMI REF-10. Still, its output noise is about 
600(lVp-p at a noise bandwidth of 1MHz (the output noise 
of the PMI REF-10 is about 3,000(1 Vp-p at 1MHz). 

So far as we know, the stability with time of the REF102 is 
significantly better than any other single-chip voltage refer- 
ence on the market. We plan more characterization of stabil- 
ity vs time, but it will probably not be available this year. 
The following preliminary data is all we have for now. The 
devices used were off-the-shelf. They were not burned-in, or 
otherwise stabilized prior to this stability test. 



Noise of a voltage reference can be reduced by filtering its 
output. Broadband noise can be reduced by the square-root 
of the reduction in noise bandwidth. Filtering the output of 
the reference to reduce the noise bandwidth by 100/1 (from 
1MHz to 10kHz, for example) can reduce the noise by 10/ 
1 (from 600(1 Vp-p to 60|iVp-p). 

The conventional circuit, shown in Figure 1 , uses a single- 
pole RC filter and a buffer amplifier. One problem with this 
circuit is that leakage current through the filter capacitor, C,, 
flows through R, resulting in DC error. Furthermore, 
changes in leakage with temperature result in drift. The 
relatively low RC time constants often needed dictate large 
capacitor values prone to this problem. 



■15V 



V+ 

REF102 

10V 
Out 

Com 




OPA27 

+ 



»+10V n 



FIGURE 1. Voltage Reference with Conventional Filter. 



REF102CM +10.0V REFERENCE STABILITY vs TIME 

T 1= 25°C, V s = +15V. 



UNIT 


V om CHANGE 
FROM 1 HR 
TO 168 HRS 
[ppm] 


V 0UT CHANGE 
FROM 1 HR 
TO 1008 HRS 
[ppm] 


V 0UT CHANGE 
FROM 1 HR 
TO 2016 HRS 
[ppm] 


V 0UT CHANGE 
FROM 1 HR 
TO 3072 HRS 
[ppm] 


^oui CHANGE 
FROM 1 HR 
TO 5136 HRS 
[ppm] 


V OUT CHANGE 
FROM 1 HR 
TO 14205 HRS 
[ppm] 


1 


6.8 


5.5 


7.1 


4.7 


8.2 


11.7 


2 


5.1 


1.0 


1.2 


-2.1 


0.1 


1.3 


3 


9.4 


6.5 


3.2 


1.0 


1.8 


2.0 


4 


9.6 


6.9 


7.7 


5.6 


7.6 


10.3 


5 


12.9 


7.8 


9.6 


6.7 


9.5 


12.8 


6 


10.5 


6.4 


5.3 


3.0 


5.4 


9.4 


7 


10.3 


5.7 


6.2 


3.7 


5.8 


8.2 


8 


17.0 


14.5 


12.9 


9.2 


9.9 


13.7 


9 


6.2 


5.1 


3.8 


1.7 


2.7 


4.1 


10 


7.1 


1.7 


1.3 


0.1 


1.0 


2.4 


11 


13.0 


9.6 


9.6 


10.0 


13.0 


16.5 


12 


7.5 


4.7 


3.9 


4.2 


5.0 


7.4 


13 


13.0 


9.5 


10.4 


8.2 


9.9 


13.7 


14 


4.2 


3.0 


0.5 


-0.3 


4.2 


2.8 


15 


7.3 


4.3 


2.6 


1.8 


4.1 


3.9 



CO 

a> 

X2 

E 



c 

a> 

"5 
m 

c 
o 

CO 

o 

Q. 

a. 
< 



■"1990 Burr-Brown Corporation 



AB-003A 



Printed in U.S.A. March. 1991 



noise 01 tne ouirer amplitier. 1 he noise of the buffer ampli- 
fier acts at the buffer's full unity-gain bandwidth adding to 
the output noise of the circuit. Even if the noise at the output 
of the RC filter is zero, the noise added by the buffer can be 
intolerable in many applications. The improved filter, shown 
in Figure 2, solves both problems. 



1 



+15V 



V+ 

REF102 

10V 
Out 

Com 




50Q C, 
.1uF 



-O +10V OUT 



Tantalum 



FIGURE 2. Voltage Reference with Improved Filter. 



both the voltage reference and the buffer is filtered. Since 
the filter is in the feedback loop of the buffer amplifier, C, 
leakage current errors reacting with R, are divided down to 
an insignificant level by the loop gain of the buffer amp. The 
feedback also keeps the DC output impedance of the im- 
proved filter near zero. Also, leakage through C 2 is negli- 
gible since the voltage across it is nearly zero. 

At high frequency, the output impedance of the improved 
filter is low due to C,. The reactance of a 1|J.F capacitor is 
0.1 6£2 at 1MHz. For an A/D converter reference, connect C, 
as close to the reference input pin as possible. 

The improved filter can drive large capacitive loads without 
stability problems. Just keep (C L0AD + C,) • R, < 0.5 • ^ • C r 

There is one caution with the improved filter. Although the 
output impedance is low at both high frequencies and DC, it 
peaks at midband frequencies. Reduced loop gain due to the 
R 2 , C 2 network is responsible. A peak output impedance of 
about 0.7 • R, occurs near the filter pole frequency. If lower 
midband output impedance is required, R, must be reduced 
and C, increased accordingly. 



The improved filter places the RC filter at the output of the 
buffer amplifier. Reference noise is filtered by a single pole 
of f WB = 2»7t»R 1 »C 1 . The R 2 , C 2 network assures amplifier 
loop stability. Set R 2 ♦ C 2 = 2 • R, • C, to minimize amplifier 
noise gain peaking. Since buffer amplifier bias current flows 
through R,, keep the value of R 2 low enough to minimize 
both DC error and noise due to op amp bias-current noise. 
Also, load current flows in R r The resulting voltage drop 
adds to the required swing at the output of the buffer 
amplifier. Keep the voltage drop across R, low, e.g. less than 
IV at full load, to prevent the amplifier output from saturat- 
ing by swinging too close to its power-supply rail. 



The information provided herein is believed to be reliable; however, BU RR-BROWN assumes no responsibility (or inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



MAKE A PRECISION -10V REFERENCE 



By R. Mark Stitt (602) 746-7445 



The need for a precision -10.0V reference arises often. For 
example, the best way to get a 0V to +10V output from a 
CMOS MDAC is to use a -10V reference (see Figures 4-6). 
ADI/PMI has the REF-08 -10V reference, but it has limited 
performance. Although Burr-Brown offers no -10V refer- 
ence, the REF102 precision +10.0V reference can be accu- 
rately converted to a precision -10.0V reference. The circuit 
is simple and requires no precision components. The 2.5ppm/ 
°C temperature drift of the Burr-Brown REF102 is twenty 
times better than the 50ppm/°C best grade of the PMI REF- 
08. (Even our lowest grade is five times better.) 

The simplest approach for converting a REF102 into a 
-10.0V reference is shown in Figure 1. The only extra 
component is a resistor connected to -V s . This circuit 
is useful, but has limitations. Maximum expected load cur- 
rent plus maximum reference quiescent current must be 
supplied by the resistor at minimum -V s . Changes in current 
resulting from load and power supply variations must be 
driven by the reference. The excess current through the 
reference reduces its accuracy due to drift from self-heating 
and thermal feedback. Changes in reference output current 
due to power-supply variations translate into line regulation 
error. Voltage reference load regulation is not usually as 
good as line regulation. Finally, the output impedance due to 
the resistor pull-down causes settling problems with dy- 
namic loads. 





2 0+V s (1.4Vto26V) 




V+ 
REF102 




6 

r 


10V 
Out 






Gnd 






4 | m O -10V Out 
™% ' L 1.4 <(f^-l L )< 5.4mA 

6 -15V VRs ; 



FIGURE 1. Simple -10V Reference. 

The circuit shown in Figure 2 solves these problems. As in 
Figure 1 , no precision resistors are needed. The error con- 
tributed by the op amp is negligible (the OPA27 0.6(J.V/°C 
V os /dT adds only 0.06 ppm/°C drift to the -10V reference). 
As a bonus, the circuit incorporates noise filtering. 




v+ 
REF102 

10V 
Out 



Gnd 



-O -10V Out 



FIGURE 2. Improved -10V Reference. 

To understand how the circuit works, notice that the refer- 
ence is in the feedback loop of the op amp. The op amp 
output forces the Gnd connection of the reference to exactly 
-10.0V so that the voltage at the op amp inverting input is 
the same as at its noninverting input (ground). Since no 
current flows into the op amp input, the reference output 
current remains at zero, eliminating voltage reference ther- 
mal feedback or load regulation errors. The Rj, C\ network 
assures loop stability and provides noise filtering. Reference 
noise is filtered by a single pole of f_ 3dB = 1/(2 • n • Ri • Ci). 
Bias current flowing through ^ can produce DC errors and 
noise. If a lower filter pole is needed, keep ^ = 2k£2 and 
increase C] to preserve accuracy. 




20kQ- 



R 2 

son 




+V S (1.4V to 26V) 



Gnd 



-O -10V Out 



+r 10mF 

I Tantalum 



FIGURE 3. Improved -1 0V Reference with Improved Filter, ,j£ 



with V 0UT Trim. 



n 
E 

3 



3 
ffi 

C 

o 

eo 
o 



a. 
a 
< 



1990 Burr-Brown Corporation 



AB-004B 



Printed in U.S.A. June, 1991 



>+Vc 



V+ 




-10V 




Reference 




-10V 




Com 





DAC7541A 

0-1 mA 



Bit1 -Bit 12 




+ 0to+10V 
Out 



FIGURE 4. Precision 0V to +10V Output DAC. 

Figure 3 shows an improved filter and a provision for output 
voltage adjustment. The 20k£2 pot can be used for fine 
adjustments or to increase the output to -10.24V for lOmV 
per 10-bit LSB — ideal in many binary DAC applications. 
The improved filter: 

1 . Provides low output impedance at high frequency for 
driving dynamic loads, 

2. Improves noise filtering, and 

3. Drives large capacitive loads — see AB-003. 



Figure 4 shows the preferred way to connect a CMOS 
MDAC for a to +10V output. This approach is less 
expensive and provides better accuracy than the other ap- 
proaches shown below. 

The circuit shown in Figure 5 is commonly used to get a 
to +10V output with a CMOS MDAC. The disadvantage 
with this circuit is that it requires an extra op amp and 
pair of precision resistors for each DAC. Also, settling 
time increases because two amplifiers must settle in the 
signal path. For good settling time, both amplifiers must be 
fast settling. Then settling time increases by the square- 
root-of-the-sum-of-the-squares of settling time for each 
amplifier. 

The circuit shown in Figure 6 can also be used to get a 
to +10V output from a CMOS MDAC. The problem with 
this circuit is nonlinearity due to code-dependent voltage 
across the switches within the DAC. Using a 2.5V reference 
and gain at the output, as shown, mitigates this error, but 
you still need a pair of precision resistors for each DAC. 
The appropriate use for this circuit is in +5V single-supply 
applications. With a 2.5V reference and a unity-gain, single- 
supply buffer, the output will be to +2.5V. 



>+v. 



v+ 




+10V 




Reference 




+10V 




Com 




± 





DAC7541A 10Wf 

I — vW- 

0-1 mA Rfb n 



V RFF 



Bit 1 -Bit 12 




10kfl 
0.01% 



0to+10V 
Out 



FIGURE 5. Another 0V to +10V Output DAC. 



v+ 

+2.5V 
Reference 
+2.5V 



Com 



X 




DAC7541A V REF 
Outi 



Bit 1 -Bit 12 



10kn 
0.01% 




0to+10V 
Out 



FIGURE 6. Single Supply 0V to +10V. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR - BROWN ®i- — — - - — - — — - — ' - ■ - - - mm.m 127 



IMM1 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



Make A Precision +10V Reference 

By R. Mark Stitt, (602) 746-7445 



Many systems require the combination of both a positive and 
a negative precision 10.0V reference. ADI offers several 
hybrid +10V references. Although Burr-Brown offers no 
+10V reference at this time, we do have some simple two- 
chip solutions which are accurate and can be more cost 
effective. (The lowest cost grades of ADI's ±10V references 
are priced at $37.25 (AD2702) and $42. 10 (AD27 12) each in 
25+ quantities.) 

Figure 1 shows one two-chip solution. It uses the super- 
stable REF102 +10.0V precision reference and an INA105 
difference amplifier connected as a precision unity gain 
inverting amplifier. The REF102CM has 2.5ppm/°C max 
drift.. The INA105BM adds drift to the -10.0V output of 
lppm/°C max due to V 0S /dT and 5ppm/°C due to gain drift. 
The V OUT error of the REF102CM is ±2.5mV max. The 
INA105BM adds ±10mV max error to the -10.0V reference. 



i +15V 



v+ 

REF102 

10V 
Out 

Com 



-O +10VOut 



-yhhht-^- 



25k£2 



25kn 



25kn 



25k£2 




INA105 



O -10V Out 



FIGURE 1. Precision Two-Chip +10.0V Reference. 



Both of the V OUT errors are adjustable to zero as shown in 
Figure 2. Because the adjustment range is small, instability 
in the trim components is negligible. Since the +V OUT ad- 
justment affects -V 0UT , adjust +V 0UT first. 

If you need a lppm/°C reference, use the REF101 as shown 
in Figure 3. The REF101 contains the precision resistors 
needed for the -10V inverter. For a +10.0V reference, the 
only additional component needed is an op amp. The 0.6(iV/ 
°C V 0S /dT of the OPA27AM adds a negligible 0.06ppm/°C 
drift to the negative reference. 

For lowest parts cost, consider the ±10V reference shown in 
Figure 4. The unity-gain-inverting amplifier in this circuit 
uses 1% resistors and a 100£2 pot to trim the -10.0V 
reference output. When using standard 1% film resistors, a - 
V 0UT drift of 50ppm/°C or more should be expected. 

TheREFlOl and REF102 are buried-zener-based references. 
They have better stability and much lower noise than stan- 
dard band-gap-based voltage references. Still, there are in- 
stances when even lower noise is required. The standard way 
to lower noise is to lower the noise bandwidth at the output 
of the reference by filtering (see Application Bulletin 3). 

The circuit shown in Figure 5 includes noise reduction filters 
on both the +10V and -10V reference outputs. The improved 
filter design shown has several advantages: 

1) low output impedance at high frequency for driving 
dynamic loads, 

2) improved noise filtering, and 

3) ability to drive large capacitive loads. 



v+ 

10V 
Out 
REF102 
Trim 

Com 



20kQ . 



•10kn 



+10V 
Adj 



20£i; 



.ikn 



20fT 



-10V 
Adj 



25kn 



25kQ 



25kn 



25kn 




INA105 



10k£i 



-O +10VOut 
-O -10V Out 



I 

E 



o 

o 

a. 
a. 
< 



FIGURE 2. Precision Two-Chip +10V Reference with ±V Trim. 



s 1990 Burr-Brown Corporation 



AB-005 



Printed in U.S.A. March, 1990 




FIGURE 3. Precision lppm/°C +10V Reference. FIGURE 4. ±10V Reference Using 1% Resistors. 



^2A 
"MA 



iokn 




FIGURE 5. Precision +10.0V Reference with Output 
Filtering. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BU RR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



129 



Make a -10V to +10V Adjustable Precision Voltage Source 



By R. Mark Stitt, (602) 746-7445 



Many situations require a precision voltage source which 
can be adjusted through zero to both positive and negative 
output voltages. An example is a bipolar power supply. 
Have you ever adjusted your unipolar lab supply down to 
OV, then swapped the output leads and adjusted it back up to 
get a negative voltage output? What happened to your circuit 
when the input from the low impedance source went open 
circuit? Were you able to actually adjust the output to OV, or 
did a small voltage offset limit the range? This precision 
bipolar voltage source can solve these problems. 

Perhaps the most obvious implementation of a bipolar volt- 
age source would be to use a bipolar voltage reference. 



v, N o- 



iokn : 

Linear - 



INA105 
Difference Amp 



VvV^ 



25kQ 
25kn 




25kf! 



+V| N tO-V| N 



-V IN , Slider at Bottom of Pot. 



FIGURE 1. -1.0V/V to +1.0V/V Linear Gain Control Am- 
plifier. 



However, a simpler solution is to use a single voltage 
reference and a precision unity-gain inverting amplifier. If 
you use a precision difference amplifier for the unity-gain 
inverting amplifier, the circuit requires just two chips and a 
potentiometer. 

To understand how the circuit works, first consider the - 
1.0 V/V to +1.0V/V linear gain control amplifier shown in 
Figure 1. An INA105 difference amplifier is used in a unity- 
gain inverting amplifier configuration. A potentiometer is 
connected between the input and ground. The slider of the 
pot is connected to the noninverting input of the unity-gain 
inverting amplifier. (The noninverting input of a unity-gain 
inverting amplifier would normally be connected to ground.) 
With the slider at the bottom of the pot, the circuit is a 
normal precision unity-gain inverting amplifier with a gain 
of -1.0V/V +0.01% max. With the slider at the top of the 
pot, the circuit is a normal precision voltage follower with a 
gain of +1.0V/V ±0.001% max. With the slider in the center, 
there is equal positive and negative gain for a net gain of 0V/ 
V. The accuracy between -1.0V/V and +1.0V/V will nor- 
mally be limited by the accuracy of the pot. Precision 10- 
turn pots are available with 0.01% linearity. 

The -1.0 V/V to +1.0V/V linear gain control amplifier has 
many applications. With the addition of a precision +10.0V 
reference as shown in Figure 2, it becomes a -10V to +10V 
adjustable precision voltage source. 



v+ 

REF102 
10V 
Out 

Gnd 



iok£i : 

Linear - 



■ +10V, Slider at Top of Pot. 
= 0V, Slider at Center of Pot. 
= -10V, Slider at Bottom of Pot. 



INA105 
Difference Amp 



25k£l 
25kfl 



VV\A— 1 




25kn 



-O Vout = 
+10Vto-10V 



I 

E 
c 



o 

o 

Q. 



FIGURE 2. -10V to +10V Adjustable Precision Voltage Source. 



e 1990 Burr-Brown Corporation 



AB-O06 



Printed in U.S.A. April, 1990 



In many instances adjustable voltage sources need the ability 
to drive high-capacitance loads such as power-supply bypass 
capacitors. The additional circuitry needed to drive high 
capacitance is shown in Figure 3. For stability, keep C L0AD «R 3 
< 0.5«R,«C,. Since access to the op amp inverting input is 
needed, the unity-gain inverting amplifier is made with an 
op amp and discrete resistors. For precision, R, and R 2 must 
be accurately matched. Also, load current flows in R y The 



resulting voltage drop adds to the required swing at the 
output of the op amp. Keep the voltage drop across R 3 low 
— less than IV at full load — to prevent the amplifier output 
from swinging too close to its power-supply rail. 

For applications with substantial volume (e.g. 5k ea/year) a 
version of the INA105 with the op amp inverting input 
brought out is available as a special (2A660). Inquire with 
marketing about price and delivery. 



V 0UT - +10V, Slider at Top of Pot. 
v 0UT - OV, Slider at Center of Pot. 
V OUT = -10V. Slider at Bottom of Pot. 




FIGURE 3. -10V to +10V Adjustable Precision Voltage Source with High Capacitance-Load Drive Capability. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR -BROWN 




APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



LOW POWER SUPPLY VOLTAGE OPERATION OF REF102 10.0V 
PRECISION VOLTAGE REFERENCE 

By R. Mark Stitt (602) 746-7445 



Two of the most important specifications for a voltage 
reference are noise and stability with time. The zener-based 
REF102 10.0V voltage reference has much better noise and 
stability than band-gap-based references. 

An advantage that band-gap-based references have in some 
applications is the ability to operate from lower voltage 
power supplies. This is because the basic band gap voltage 
is approximately 1.2 V as compared to 6 V to 8 V for a zener 
diode. As a 10.0V reference, the REF102 requires a mini- 
mum 1 1.4V V s . If the higher performance of a REF102 is re- 
quired, there are several options for operation on lower 
supply voltages. 

If a negative supply is available, it may be possible to oper- 
ate the REF102 on a positive supply as low as 4.5V. Another 
option is to use one of the simple DC/DC converter circuits 
shown to operate the REF102 from a single +5V power 
supply. 

The simplest option for reduced supply operation of a 
REF102 is to add a unity-gain inverter to make a ±5.0V 



v+ 
(6.4V min) 



V+ 

REF102 

+10V 
Out 

Gnd 




-O +5.0V Out 



-O-5.0V Out 



FIGURE 1 . ±5.0V Reference Using REF102 Can Operate on 
+V S = +6.4V, -V s = -8V. 



reference as shown in Figure 1. This allows the REF102 to 
be used on +9V power supplies, for example. The minimum 
voltage for V+ is actually 6.4V (the output of the REF102 
can operate within 1.4V of its positive supply). 

The minimum negative supply depends on the amplifier 
used for the unity-gain inverter. With an INA105 difference 
amp used for the unity-gain inverter, the negative power 
supply must be at least -8V. 

To operate the REF102 on a minimum +V S of 4.5V, use an 
INA106 gain-of-10 difference amplifier for the inverter as 
shown in Figure 2. With the INA106, the reference outputs 
are +1.0V and -9.0V. The 4.5V minimum +V S rating is due 
to the output swing limit of the INA106. The negative 
supply must be at least -12V. 



v+ 
(4.5V min) 



V+ 

REF102 

+10V 
Out 



Gnd 



R 2 

iookn 




INA106 



FT 



-O +1 .0V Out 



-O-9.0V Out 



V- 
(-12V min) 



FIGURE 2. + 1 .0V, -9.0V Reference Using REF 1 02 Can Op- 
erate on +V S = +4.5 V, -V s = -12V. 



s 1990 Burr-Brown Corporation 



AB-011 



Primed in U.S.A. June, 1990 



When only a single +5V power supply is available, the 
REF102 can be operated by boosting the 5 V supply with one 
of the many inexpensive DC/DC converter chips available. 

A single 5V supply can be boosted to a regulated 15V with 
a flyback converter as shown in Figure 3. The Maxim 
MAX643 is basically a self-contained DC/DC converter in 
an 8-pin plastic DIP. The only additional components needed 
to convert 5V to a regulated 15V are a single external 
inductor and a few bypass capacitors. R 6 and C 3 add addi- 
tional ripple filtering. Good results were obtained with an 
inductor made from 16 turns of #16 wire on a TDK HC52 
T5- 10-2.5 core. See the Maxim data sheet for more informa- 
tion regarding the DC/DC converter. 

Another option is to boost a single 5V supply to ±10V to 
drive a ±5.0V reference as shown in Figure 4. The Maxim 
MAX68 1 is a completely self-contained DC/DC converter 
using charge-pump techniques to convert 5V to +10V. 



1mH 
16 Turns 
#26 Wire on TDK 
HC52T5-1 0-2.5 



"O +5V 



10uF 



NC NC 



nm 



MAXIM 
MAX643 



1uF ; 
Tantalum 



NC 



C 3 

iuf ; 

Tantalum 



V+ 

REF102 

+10V 
Out 



Gnd 



i-10.0VOut 

Q 



4 



FIGURE 3. +10.0V Reference Using REF102 Can Operate 
on Single +5V Power Supply. 



Q +5V 



NC 

NC 

NC 

NC 

NC 

NC 
10V Out 



MAXIM 
MAX681 



10uF 



0.1uF 



■10V Out 



V+ 

REF102 

+10V 
Out 

Gnd 



NC - Make No External Connection 




INA105 



+5.0V 
Reference 
Out 



-5.0V 
Reference 
Out 



FIGURE 4. ±5.0V Reference Using REF102 Can Operate on 
Single +5V Power Supply. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



By Bruce Trump and R. Mark Stitt (602) 746-7445 



133 



Although low-pass filters are vital in modern electronics, 
their design and verification can be tedious and time 
consuming. The Burr-Brown FilterPro™ program makes 
it easy to design unity-gain low-pass active filters. The 
program supports the most commonly used all-pole fil- 
ters: Butterworth, Chebyshev, and Bessel. 

Butterworth — maximally flat magnitude. This filter has 
the flattest possible pass-band magnitude response. At- 
tenuation is -3dB at the design cutoff frequency. Attenu- 
ation above the cutoff frequency is a moderately steep 
-20dB/decade/pole. The pulse response of the Butterworth 
filter has moderate overshoot and ringing. 

Chebyshev — equal ripple magnitude. (Sometimes trans- 
lated Tschebyscheff or Tchevysheff). This filter response 
has steeper attenuation above the cutoff frequency than 
Butterworth. This advantage comes at the penalty of 
amplitude variation (ripple) in the pass-band. Unlike 
Butterworth and Bessel responses, which have 3dB at- 
tenuation at the cutoff frequency, Chebyshev cutoff fre- 
quency is defined as the frequency at which the response 
falls below the ripple band. For even-order filters, all 
ripple is above the OdB DC response, so cutoff is at OdB — 
see Figure la. For odd-order filters, all ripple is below the 
OdB DC response, so cutoff is at -(ripple) dB — see Figure 
lb. For a given number of poles, a steeper cutoff can be 
achieved by allowing more pass-band ripple. The 
Chebyshev has even more ringing in its pulse response 
than the Butterworth. 



Bessel — maximally flat delay, (also called Thomson). 
Due to its linear phase response, this filter has excellent 
pulse response (minimal overshoot and ringing). For a 
given number of poles, its magnitude response is not as 
flat, nor is its attenuation beyond the -3dB cutoff fre- 
quency as steep as the Butterworth. It takes a higher-order 
Bessel filter to give a magnitude response similar to a 
given Butterworth filter, but the pulse response fidelity of 
the Bessel filter may make the added complexity worth- 
while. 

SUMMARY 

Butterworth 

Advantages — Maximally flat magnitude response in the 
pass-band. 

Disadvantages — Overshoot and ringing in step response. 
Chebyshev 

Advantages — Better attenuation beyond the pass-band than 
Butterworth. 

Disadvantages — Ripple in pass-band. Even more ringing 
in step response than Butterworth. 

Bessel 

Advantages — Excellent step response. 
Disadvantages — Even poorer attenuation beyond the pass- 
band than Butterworth. 



FilterPro™ , Burr-Brown Corp. 



f10 



65 

B -10 



% - 20 
cc 

£ -30 

E 

-40 



-50 
f c /1 00 



FILTER RESPONSE vs FREQUENCY 





















































































Ri[ 


>pl 


8 






































4 


■P 


)le( 
3dB 


Jhebys 


lev 
























Ripple 
































































































































































V 







































f c 

Normalized Frequency 



10f n 



FIGURE la. Response vs Frequency of Even-Order 
(4-pole), 3dB-Ripple Chebyshev Filter 
Showing Cutoff at OdB. 





+10 







CD 




;o 


-10 


CD 




CO 




o 

CL 


-20 


CO 


05 

EE 




Filter 


-30 




-40 




-50 



f c /1 00 



FILTER RESPONSE vs FREQUENCY 





















































































1 
































































































"t 


Ripple 










5 


-Pole C 


hebyshev 




































3dB Ripple 































































































































































































































































































































fc/10 f c 
Normalized Frequency 



10f, 



FIGURE lb. Response vs Frequency of Odd-Order 
(5-pole), 3dB-Ripple Chebyshev Filter 
Showing Cutoff at -3dB. 



CL 
Q. 
< 



®1990 Burr-Brown Corporation 



AB-017C 



Printed in U.S.A. August, 1991 



Even-order filters designed with this program consist of 
cascaded sections of Sallen-Key complex pole-pairs. 

Odd-order filters contain an additional real-pole section. 
Figures 2 to 5 show the recommended cascading arrange- 
ment. Lower Q stages are placed ahead of high Q stages 
to prevent op amp output saturation due to gain peaking. 
The program can be used to design filters up to 7th order. 

USING THE FilterPro™ PROGRAM 

With each data entry, the program automatically calcu- 
lates values for filter components. This allows you to use 
a "what if spreadsheet-type design approach. For ex- 
ample, you can quickly determine, by trial-and-error, how 
many poles are needed for a given roll-off. 

RESISTOR VALUES 

The program automatically selects standard capacitor val- 
ues and calculates exact resistor values for the filter you 
have selected. In the "1% display" option, the program 




FIGURE 2. Real Pole Section (unity-gain, first-order 
Butterworth) f_ MB = l/(2rc RjC,) 



calculates the closest standard 1% resistor values. To 
select standard 1% resistor values, use the arrow keys to 
move the cursor to the Display menu selection. Then press 
<ENTER>. Because the program selects the closest 1% 
resistor for one resistor in each pole-pair, and then calcu- 
lates the exact value for the second resistor before selecting 
the closest 1% value for the second resistor, it produces 
the most accurate filter design that can be implemented 
with 1% resistors. 

Using the "Scale Resistors" menu option allows you to 
scale the computer-selected resistor value to match the 
application. The default value of lOkQ is suggested for 
most applications. 

Higher resistor values, e.g. 100k£2, can be used with FET- 
input op amps. At temperatures below about 70°C, DC 
errors and excess noise due to op amp input bias current 
will be small. However, noise due to the resistors will be 
increased by the square-root of resistor increase. 



V,nO 



Optional 
Buffer 




Complex Pole-Pair Section 
^2A \— 



T 

'I 




A 3 



FIGURE 3. Second-Order, Unity-Gain, Low-Pass Filter 
Using Sallen-Key Configuration for Com- 
plex Pole-Pair. 



v IN o 



Optional 
Buffer 




Complex Pole-Pair Section A 




Complex Pole-Pair Section N 



VVV^' R 2* 




o v 



FIGURE 4. Even-Order, Unity-Gain, Low-Pass Active Filter Using Cascaded Sallen-Key Complex Pole-Pairs. 



V,nO 



Optional 
Buffer 




Real Pole Section 




Complex Pole-Pair Section A 



1 




R 1X 



Complex Pole-Pair Section N 
^2x \L 



--MA - ' R 2X 

WW — t- 




FIGURE 5. Odd-Order, Unity-Gain, Low-Pass Active Filter Using One Real Pole Followed by Cascaded Sallen-Key 
Complex Pole-Pairs. 



135 



Lower resistor values, e.g. 500£2, are a better match for 
high-frequency filters using the OPA620 op amp. 

Capacitor Values 

Compared to resistors, capacitors with tight tolerances are 
more difficult to obtain and can be much more expensive. 
Using the "capacitor menu" option allows you to enter 
actual measured capacitor values. The program will then 
select exact or closest standard 1 % resistor values as before. 
In this way, an accurate filter response can be assured with 
relatively inexpensive components. 

If the common-mode input capacitance of the op amp used 
in a filter section is more than approximately 0.25% of C,, 
it must be considered for accurate filter response. A capaci- 
tor menu option allows you to change the values of pro- 
gram-selected capacitors as explained earlier. To compen- 
sate for op amp capacitance, simply add the value of the op 



amp common-mode input capacitance to the actual value of 
C,. The program then automatically recalculates the exact 
or closest 1% resistor values for accurate filter response. 

Op Amp Selection 

It is important to choose an op amp that can provide the 
necessary DC precision, noise, distortion, and bandwidth. 

In a low-pass filter section, maximum gain peaking at f n 
(the section's natural frequency) is very nearly equal to Q. 
As a rule of thumb, for a unity-gain Sallen-Key section, 
the op amp bandwidth should be at least 100 • Q 3 • f n . For 
a real-pole section, op amp bandwidth should be at least 
50 • f . For example, a 20kHz 5-pole Butterworth filter 
needs a 8.5MHz op amp in the Q = 1.62 section. 

To aid in selection of the op amp, a program option can 
display f and Q for each section. Press <ENTER> in the 
Display option of the menu. Although Q is formally 



Attach Disk Sleeve Here. 



Call (602) 741-3978 to down-load a DOS-compatible executable file. Down-load the 
FILTER 1 file from the components, analog circuit functions area. File transfers are supported 
by XMODEM, Kermit, ASCII and Sealink protocols. Communications settings are 300/ 
1200/2400 baud, 8-N-l. 

Or, 

Call John Conlon, Applications Engineer 
(800) 548-6132 for a DOS compatible 5-1/4" disk. 



defined only for complex poles, it is convenient to use a 
Q of 0.5 for calculating the op amp gain required in a real- 
pole section. 

The slew rate of the op amp must be greater than 
71 • V 0i>[j • filter bandwidth for adequate full-power 
response. For example, a 100kHz filter with 20Vp-p 



OP AMP SELECTION GUIDE, (in order of increasing slew rate.) 

T A = 25°C, V S =±15V, specifications typ, unless otherwise noted, mirvmax specifications are for high-grade model. 



OP AMP 
MODEL 


BW 
typ 
(MHz) 


FPR 

typ 

(kHz) 


SR 
typ 

(V/us) 


max 

m 


Vos/dT 
max 

(nv/°C) 


NOISE 
at 10kHz 

(nVA/Hz) 


C i" 

^CM 

(pF) 


OPA177 


0.6 


3 


0.2 


10 


±0.1 


8 


1 


OPA27 


8 


30 


1.9 


25 


±0.6 


2.7 


1 


OPA2107' 2 ' 
dual 


4.5 


280 


18 


500 


±5 


8 


4 


OPA2604< 2 > 
dual 


10 


400 


25 


2000 


±5 typ 


10 


10 


OPA602' 21 


6 


500 


35 


250 


±2 


12 


3 


OPA404' 2 ' 
quad 


6 


500 


35 


1000 


±3 typ 


12 


3 


OPA627' 21 


16 


875 


55 


100 


±0.8 


4.5 


7 


OPA620 
(V, = ±5V) 


300 


16MHz 
(5Vp-p) 


250 


500 


±8 typ 


2.3 
(at 1MHz) 


1 



NOTES: (1) Unless otherwise noted, FPR is full power response at 20vp-p as calculated from slew rate. (2) These op amps have FET inputs. (3) Common- 
mode input capacitance. 



output requires an op amp slew-rate of at least 
6.3V/u.s. Burr-Brown offers an excellent selection of 
op amps which can be used for high performance 
active filters. The guide below lists some good 
choices. 



CAPACITOR SELECTION 

Capacitor selection is very important for a high-perfor- 
mance filter. Capacitor behavior can vary significantly 
from ideal, introducing series resistance and inductance 
which limit Q. Also, nonlinearity of capacitance vs volt- 
age causes distortion. 

Common ceramic capacitors with high dielectric con- 
stants, such as "high-K" types can cause errors in filter 
circuits. Recommended capacitor types are: NPO ceramic, 
silver mica, metallized polycarbonate; and, for tempera- 
tures up to 85°C, polypropylene or polystyrene. 

THE UAF42 UNIVERSAL ACTIVE FILTER 

For other filter designs, consider the Burr-Brown UAF42 
Universal Active Filter. It can easily be configured for a 
wide variety of low-pass, high-pass, or band-pass filters. It 
uses the classical state- variable architecture with an inverting 
amplifier and two integrators to form a pole-pair. The 
integrators include on-chip lOOOpF, 0.5% capacitors. This 
solves one of the most difficult problems in active filter 
implementation — obtaining tight tolerance, low-loss ca- 
pacitors at reasonable cost. 



Simple design procedures for the UAF42 allow implemen- 
tation of Butterworth, Chebyshev, Bessel, and other types 
of filters. An extra FET-input op amp in the UAF42 can be 
used to form additional stages or special filter types such as 
band-reject and elliptic. The UAF42 is available in a stan- 
dard 14-pin DIP. For more information about the UAF42 
request Burr-Brown Product Data Sheet PDS-1070. 

EXAMPLES OF FILTER RESPONSE 

Figures 6a and 6b show actual measured magnitude re- 
sponse plots for 5th-order 20kHz Butterworth, 3dB 
Chebyshev and Bessel filters designed with the program. 
The op amp used in all filters was the OPA627. As can be 
seen in Figure 5, the initial roll-off of the Chebyshev filter 
is fastest and the roll-off of the Bessel filter is the slowest. 
However, each of the 5th-order filters ultimately rolls off 
at -N • 20dB/decade, where N is the filter order (-lOOdB/ 
decade for a 5-pole filter). 

The oscilloscope photographs show the step response for 
each filter. As expected, the Chebyshev filter has the most 
ringing, while the Bessel has the least. 





-10 
-20 
-30 
-40 
-50 
-60 
-70 
-80 
-90 



















































c 
t 




s 


















































- 


























Bi 


tte 
























































3d 


3 C 






shev- 







































































































200 



1k 



10k 

Frequency (Hz) 



200k 



FIGURE 6a. Gain vs Frequency for 5th-Order 20kHz 
Butterworth, 3dB Chebyshev, and Bessel 
Unity-Gain Low-Pass Filters Showing 
Overall Filter Response. 



o 

-3 
-6 
-9 
-12 
-15 
-18 
-21 
-24 
-27 



400 























































= 




/ 






































































vessel — 


V 


V 




































A 
























B 


utte 


r 


worth 






































i 






















3 


IE 


L 


h 


St 


>i 


shev — « 


— 


\ 












- 
























v 




































1 



1k 



10k 20k 



40k 



Frequency (Hz) 



FIGURE 6b. Gain vs Frequency for 5th-Order 20kHz 
Butterworth, 3dB Chebyshev, and Bessel 
Unity-Gain Low-Pass Filters Showing 
Transition Band Detail. 





FIGURE 7. Step Response of 5th-Order 20kHz 
Butterworth Low-Pass Filter. 



FIGURE 8. Step Response of5th-Order 20kHz 3dB Ripple 
Chebyshev Low-Pass Filter. 




0.1 



0.01 



0.001 



FILTER THD, 20kHz, 5 POLE 




10 3 

Frequency (Hz) 



FIGURE 9. Step Response of 5th-Order 20kHz Bessel 
Low-Pass Filter. 



FIGURE 10. Measured Distortion for the Three 20kHz 
Low-Pass Filters. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN 
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject 
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not 
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 



BURR - BROWN ' 

IMMI 



'APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: TO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 

FAST SETTLING LOW-PASS FILTER 

By Rod Burt and R. Mark Stitt (602) 746-7445 



Noise reduction by filtering is the most commonly used 
method for improving signal-to-noise ratio. The increase in 
settling time, however, can be a serious disadvantage in 
some applications such as high-speed data acquisition sys- 
tems. The nonlinear filter described here is a simple way to 
get a four-to-one improvement in settling time as compared 
to a conventional filter. 

To understand the circuit, first consider the dynamics of a 
single-pole RC filter (Figure 1). Filtering reduces broadband 
or "white" noise by the square root of the bandwidth reduction 
as shown by the following calculation: 



2 

e n 2= Je 



e„2= |e B 2df = e B 2.f 



e„ = e B (f 2 -f,)'/2 

Where: 

e n = total noise (Vrms) 

e D = broadband noise (VWHz) 

fj, f 2 = frequency range of interest (Hz) 

In other words, if the frequency range (f 2 - f,) is reduced by 
a factor of 100, the total noise would be reduced by a factor 
of 10. 

Unfortunately, settling time depends on bandwidth. The 
penalty for the noise reduction is increased settling time. For 
a single-pole filter, the time needed for the signal to : 
any given accuracy can be calculated as follows: 

For Vq/V^ at time = t s 




FIGURE 1. Conventional Single-Pole RC Filter. 




Diodes 
1N4148 



-OV n 



"I 



• For 10kHz, C, = 1592pF. 
f^ B = 1/(2 • k • R, • C,) 



FIGURE 2. Diode-Clamped Nonlinear Filter (can improve 
0.01% settling time for a conventional filter by 
2/1 for a 20V step). 



= 1 _ e -0s/IRi-C|]) 



IN 



(— -■) 

V V, N / 



• 100 = % 

'IN 

therefore 

t s =-ln(%/100)«R, .C, 

Where: 

t s = settling time (s) 

% = percent accuracy at t s 

R, • C, = RC time constant (Q • F) or (s) 

For example, if a settling to 0.01% is needed, 

ln(0.01/100) = -9.2 

In other words, it takes 9.2 R, • C, time constants for an input 
step to settle to within 0.01% of its final value. 



NONLINEAR FILTER 

To understand how a nonlinear filter can improve settling 
time, consider the simple diode clamped nonlinear filter, 
shown in Figure 2. Settling time is improved because the 
filter capacitor, C f , is charged faster through the low forward 
biased diode impedance (R ON ) during the initial portion of a 
large input step change. When the difference between the 
input and output voltage becomes less than the forward 
biased diode drop (about 0.6V), the diode turns off and C, 
reacts with R l alone. At this point, the circuit behaves like a 
normal single-pole RC filter. 

Assuming diode R ON is negligible, the improvement in set- 
tling time depends on the ratio of the input step voltage to 
the forward biased diode voltage. For a step of -10V to 
+ 10V (a 20V step), the improvement is ln(0.60/20) or 3.5 
time constants. In other words, for a 20V step, the simple 



' 1991 Burr-Brown Corporation 



AB-022 



Primed in U.S.A. January, 1991 




• For 10kHz, C, = 1592pF. 
f^ B = 1/(2-«.R, -C,) 



FIGURE 3. Improved Nonlinear Filter (can improve 0.01% 
settling time for a conventinal filter by 4/1 for 
a 20V step). 

diode clamped nonlinear filter can improve 0.01% settling 
time from 9.2 time constants to 

(9.2) - (3.5) = 5.7 time constants. 

For smaller differences between the input step change, and 
the forward biased diode voltage, the simple diode-clamped 
nonlinear filter affords less improvement. As the step change 
approaches the forward biased diode voltage, the simple 
nonlinear filter offers no improvement. 

IMPROVED NONLINEAR FILTER 

By reducing the threshold to below one diode drop, the 
settling time can be improved for smaller inputs. The im- 
proved nonlinear filter shown in Figure 3 lets you adjust the 
threshold to a small arbitrary value by adjusting the ratio of 
R, and R r 

To see how the improved nonlinear filter works, notice that 
the op amp forces the voltage at its inverting input to be the 
same as at the noninverting input. For small differences 
between the output voltage and the input voltage, the differ- 
ence is dropped across the 10k£2 resistor, R,, and the filter 
behaves like a single-pole filter with an R, • C, time con- 
stant. The voltage divider formed by R, and R 2 amplifies the 
voltage difference across R,, as seen at the top of R 2 , by (1 
+ Rj/R,). As the voltage across the R,, R 2 divider becomes 
larger, one of the diodes (which one depends on signal 
polarity) begins to conduct, and the capacitor is rapidly 
charged through it. This occurs at a voltage difference 
between the input and output of about 0.6V/(1 + Rj/R,) or 
about 20mV with the values shown. With the diode forward 
biased, the time constant of the filter becomes very small, 
limited only by op amp slew rate or current limit. 

To determine the component values for the improved 
nonlinear filter, consider the noise-reduction requirements 
of the filter. For example, if you want to filter the noise of 
a 20V full-scale signal to 0.01% resolution, the peak noise 
must be filtered to less than 0.01% of 20V, i.e. 2m V peak. 



R 4 




* For 10kHz. C, = 1592pF. 
f^, = 1/(2 • k • R, • C,) 



FIGURE 4. Improved Nonlinear Filter with R 4 , C 3 Prefilter 
and R 3 , C 2 Network to Assure Op Amp Stability 
in Driving C,. 

A clamp threshold of ten times this peak (20m V) is an 
arbitrary but ample threshold. The component values shown 
in Figure 3 set the filter's threshold to 20m V. For a 20V step 
as before, the improvement in settling time is ln(0.02/ 
20) = 6.9 time constants. In other words, for a 20V step, the 
improved nonlinear filter can improve 0.01% settling time 
from 9.2 time constants to (9.2) - (6.9) = 2.3 time constants — 
a four-to-one improvement. 

SOME SIGNALS REQUIRE PREFILTERING 

In some instances, the input signal may have noise peaks 
above the 20m V threshold of the nonlinear filter. If the noise 
of the input signal to the nonlinear filter is greater than the 
20mV threshold, the filter will mistake the noise for a step 
input and fail to filter it out. To prevent this situation an 
input prefilter can be added to the nonlinear filter as shown 
in Figure 4. 

The prefilter's bandwidth is set by R 4 and C 3 . To minimize 
the prefilter's effect on settling time, its bandwidth is set ten 
times higher than the bandwidth of the nonlinear filter. At 
this higher bandwidth, the prefilter's effect on settling time 
is negligible, and the noise at the prefilter's output is VTO 
times greater than 2mV (a little over 6mV peak). A noise 
level of 6mV provides a comfortable margin for a 20mV 
threshold. 

ASSURE OP AMP STABILITY 

Op amps tend to become unstable and oscillate when driving 
large capacitive loads. The C 2 , R 3 network, shown in Figure 
4, assures op amp stability when driving large values of C, 




Traces 1 to 3 show settling response tor the various filters. Gain of the 
signals is 1 00V7V, so each division of the scope graticule represents 
2mV (i.e. each division = 0.01%). 

Trace 1 is a standard 10kHz single-pole RC filter. 

Trace 2 is a diode-clamped 10kHz nonlinear filter. 

Trace 3 is the improved 10kHz nonlinear filter shown in Figure 4. 

Trace 4 is the ±10V input signal at 5V/division. 



SB 


mw^Jm 

mi m 


Mm 




mm 




mm 






mg 




111 








■ril 






in 












II 






■■ 








■1 






i 

n 


■ ■ • • 

■ 








■ 








! 




I 







Trace 1 shows 10kHz single-pole filter response for a ±10mV input 
step. 

Trace 2 shows fast response for a ±1 0V input step. 



FIGURE 5. Settling-Time Response of Standard and 
Nonlinear Filters. 

through the low impedance of the forward biased diode 
network. The C 2 , R } network may not be needed if C, is small. 

When choosing the op amp for the improved filter, make 
sure it has high output drive capability for charging C, t and 
that its slew rate, settling time, and DC precision are adequate 
for the necessary filter response. The OPA627 shown has an 
excellent combination of DC precision, high slew rate, fast 
settling time and high output drive capability. The 16MHz 
bandwidth of the OPA627 gives excellent results for filters 
with -3dB bandwidths up to 100kHz. Also, notice that the 
op amp noise adds (at unity gain) to the signal noise. When 
a low noise op amp is used, this noise will be negligible in 
most instances. 

The OPA627 contributes only a 6% increase in noise to the 
minimum theoretical noise of the lOkfl resistor used in the 
filter. Remember that noise adds as the square root of the 
sum of the squares. To determine how much the 4.5nV/>/Hz 
noise of the OPA627 adds to the 12.8nV/VHz noise of the 
1 OkQ. resistor, calculate the noise of the two components and 
compare that to the noise of the resistor alone: 

V(4.5) 2 + (12.8) 2 /12.8 = 1.06, a 6% increase 

Figure 5 is a triple exposure scope photo showing the filter 
output error settling time response for the three circuits to a 
-10V to +10V input step (20V). The bandwidth of each filter 
is set to 10kHz. The settling response is in a gain of 100 so 
that each box represents 2m V, or 0.01% of a 20V step. The 
filter has settled to 0.01% when the trace is within one box 
of the base grid. 



FIGURE 6. Comparison of Large and Small Signal Step 
Response of the Improved Nonlinear Filter. 



FILTER 
TYPE 


THEORETICAL 
SETTLING TIME 
(time constants) 


THEORETICAL 
SETTLING TIME 

(us)m 


Single-Pole RC 


9.2 


147 


Diode-Clamped 
Nonlinear 


5.7 


91 


Improved 
Nonlinear 


2.3 


37 


NOTE: (1 ) Settling to 0.01 % of final value for a 1 0kHz filter. 



TABLE L Theoretical Settling Times for Various Filters. 



For a 10kHz filter, one RC time constant is 15.9|is. Ignoring 
input slew rate, and diode forward resistance (good approxi- 
mations for the 10kHz filter when using an OPA627 op amp), 
the theoretical settling times are shown in Table I. 

Notice that the actual measurements shown by the scope 
photos agree to the theoretical values within the resolution 
of the photographs. 

Figure 6 is a double exposure scope photograph of the 
improved nonlinear filter operating at a high and low signal 
level. At the low level (a ±10mV input step), the response is 
that of a 10kHz single-pole RC filter as expected. At the high 
level (a ±10V input step), the greatly improved settling 
response is observed. 



The information provided herein is believed to be reliable; however, BURR- 
BROWN assumes no responsibility for inaccuracies or omissions. BURR- 
BROWN assumes no responsibility for the use of this information, and all use of 
such information shall be entirely at the user's own risk. Prices and specifications 
are subject to change without notice. No patent rights or licenses to any of the 
circuits described herein are implied or granted to any third party. BURR- 
BROWN does not authorizeorwarrantany BURR-BROWN product foruse in life 
support devices and/or systems. 



BURR - BROWN 

imhi 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



A LOW NOISE, LOW DISTORTION DESIGN 
FOR ANTIALIASING AND ANTI-IMAGING FILTERS 



By Rick Downs (602) 746-7327 



Many customers have requested more information about the 
analog low-pass filters that appear in many of our PCM 
audio data sheets. They are used for antialiasing in front of 
ADCs or for smoothing on the output ofDACs. The following 
bulletin is an excellent primer on the subject. — Ed. 

In any digitizing system, antialiasing and anti-imaging fil- 
ters are used to prevent the signal frequencies from "folding 
back" around the sample frequency and causing false (or 
alias) signals from appearing in the signal we are attempting 
to digitize. Very often, these filters must be very complex, 
high order analog filters in order to do their job effectively. 

As sampling rates of converter systems have increased, 
however, oversampling may be used to reduce the filters' 
stopband attenuation requirements 010 '. In digital audio sys- 
tems, 4x oversampling may be used, and it can be shown (3) 
that for an antialiasing filter (which precedes the ADC), a 
simple sixth order filter may be used. For the output side, 
after the DAC, a simple third order filter may be used. 
Realizing these filters in a way that maintains extremely low 
noise and low distortion then becomes a challenge. 

Compact disk player manufacturers began using a filter 
topology that was described many years ago — the General- 
ized Immittance Converter (GIC) (4) . This topology allows 
one to easily realize active filters beginning from a passive 
filter design. In addition, the GIC filter provides extremely 
low distortion and noise, at a reasonable cost. Compared 
with more familiar feedback filter techniques, such as Sallen 
& Key filter topologies, the GIC filter can be shown to have 
superior noise gain characteristics, making it particularly 
suitable for audio and DSP type applications' 5 '. 

We use this type of filter on our demonstration fixtures for 
the PCM 1750 and PCM 1700, dual 18-bit ADC and DAC, 
respectively. When sending out schematics of these dem- 
onstration fixtures, very often the first question is, "What are 
those filters anyway?" Well, they're GIC filters, and here's 
how you design them and how they perform. Stepping 
through this design process will allow you to modify these 
designs for a different cutoff frequency for your particular 
application. A more detailed treatment of the theory behind 
these filters may be found in Huelsman and Allen <6) . 

As stated above, for oversampling digital audio applications, 
third and sixth order filters are adequate. Thus, we may 
design our first GIC filter by designing a third order filter. 
The filter characteristic most desirable for sensitive DSP 
type applications is linear-phase. The linear-phase filter is 
sometimes called a Bessel (or Thomson) filter. The linear- 
phase filter has constant group delay. This means that the 
phase of the filter changes linearly with frequency, or that 



L, 

0.9852H 



1-3 
0.3350H 



■ c 2 

' 0.8746F 



R 4 



FIGURE 1. Passive Third Order, Linear-Phase, Low-Pass 
Filter Prototype. 

the group delay is constant. These filters maintain phase 
information for sensitive DSP applications such as correla- 
tion, and preserve transient response. These characteristics 
are critical in audio applications as well, because they affect 
sound quality greatly. 

Thus, we begin the design process by selecting a passive, 
third order linear-phase filter design that will be realized 
using this active approach. The passive design shown in 
Figure 1 is neither a Butterworth nor a Bessel response; it is 
something in between. The component values for this par- 
ticular response, optimized for phase linearity and stopband 
attenuation, were found through exhaustive computer simu- 
lations and empirical analysis. Component values for stan- 
dard Butterworth and Bessel responses may be found in 
standard filter tables, such as those available in Huelsman 
and Allen (7) . This circuit is then transformed to an active 
circuit by multiplying all circuit values by 1/s, which changes 
all inductors to resistors, all resistors to capacitors, and all 
capacitors to Frequency Dependent Negative Resistors 
(FDNRs). These FDNRs have the characteristic impedance of 

1 

s 2 C 

and may be realized using the GIC circuit. Thus, L, becomes 
R,, C 2 becomes l/s 2 C 2 , L 3 becomes R 3 , and the terminating 
resistor R 4 becomes C 4 , as shown in Figure 2. 



0.9852H 



I 



R 3 



1 0.3350Q 



= s 2 C 2 
0.8746FS 



^-C 4 
~ 1F 



FDNR: units are farad-seconds (Fs) 



FIGURE 2. Filter of Figure 1 Transformed by Multiplying 
All Component Values by 1/s. 



®I991 Burr-Brown Corporation 



AB-026A 



Printed in U.S.A. March, 1991 



The FDNR is then realized by the GIC circuit shown in 
Figure 3. The value of the FDNR is determined by 

D = (R 12 • R, 4 • C, 3 • C 15 )/R u 




FIGURE 3. Frequency Dependent Negative Resistor 
(FDNR) Realized Using Generalized Immit- 
tance Converter (GIC). 



Thus by setting R u = R 12 = 1 and C 13 = C I5 = 1, D is entirely 
determined by the value of R 14 . For the FDNR of Figure 2, 
R M =0.8746£1 

The entire third order filter circuit is shown in Figure 4. This 
circuit now must be scaled in frequency to give the desired 
cutoff frequency, and then must be scaled in impedance to 
allow for the use of reasonable sized component values. 

The filter circuits found in filter tables, such as that in Figure 
1 and the active realization of this passive circuit (Figures 2 
and 4), are designed for a cutoff frequency of a> = 1 rad/s. To 
make the filter have the cutoff frequency we desire, we must 
scale it in frequency by the scaling factor 

This scaling factor is applied to all frequency-determining 
components — capacitors in this case. The example filter will 
be designed for audio, so we might consider a cutoff fre- 
quency of 20kHz. However, linear-phase filters tend to roll- 
off very slowly, causing l-2dB attenuation before the cutoff 
frequency; generally audio systems prefer to have their 
frequency response out to 20kHz to be within 0.1 dB. The 
example filter then will have a cutoff frequency of 40kHz, 
commonly used in many of today's CD players. All capaci- 
tor values are divided by the frequency scaling factor, so 
C 13 = C 15 = C 4 = 3.98uF. 



0.9852Q 




A, 




0.3350Q 




-O V, 



OUT 



J-C 4 
1F 



^ 0.87468 

: c 15 

1F 



FIGURE 4. Third Order, Linear-Phase Realization of Circuit Shown in Figure 2. 



6 



0.985212 




-O V, 



OUT 



■ c 4 

'3.98uF 



: R u 

• 0.8746Q 

- c, 5 

"3.98uF 



FIGURE 5. Circuit of Figure 4 Scaled to a 40kHz Cutoff Frequency. 




\A1 



FIGURE 6. Circuit of Figure 5 Scaled in Impedance (note use of buffer amplifier to reduce output impedance of the filter). 



The filter (Figure 5) could now be built, but the large 
capacitor values and low resistance values could pose prac- 
tical problems. To alleviate this, the impedances of the 
circuit are scaled by an impedance scale factor: 

Present C value 



Desired C value 



By choosing the desired C value as lOOOpF, Z n = 3.97xl0 3 . 
This impedance scaling factor then is multiplied by all 
resistor values to find the new resistor values, and divides all 
the capacitor values, taking them from the present values to 
the desired capacitance. 

The final filter design is shown in Figure 6. Since the output 
impedance of this filter is relatively high, it's a good idea to 
buffer the output using an op amp voltage follower. Ampli- 
tude and phase response of this filter is shown in Figure 7a. 
Figure 7b is a closer look at the amplitude response in the 
passband — the frequency response is flat well within 0.1 dB 
out to 20kHz. 

Figure 7c is a plot of the frequency response of the filter 
(solid line) and the filter's deviation from linear phase 
(dotted line). Note the phase scale; the phase response is 
well within 0.1° of linear phase in the lkHz-20kHz region, 
where the ear is most sensitive to phase distortion. 

Figure 7d is a plot of the total harmonic distortion plus noise 
(THD + N) of this filter versus frequency. At about -108dB, 
this would be suitable for digital systems with true 18-bit 
converter performance! 

To make a sixth order filter, you can repeat the design 
process above from a passive realization and directly imple- 
ment a filter. This implementation is very sensitive to the 
gain-bandwidth product (GBW) match of all of the op amps 
used, however, for a 40kHz cutoff frequency, an op amp 
with extremely high GBW would be required. An example 



of a sixth order, 40kHz Butterworth filter realized in this 
fashion is shown in Figure 8, but its frequency response 
(Figure 9) is less than hoped for due to the GBW limitations 
described above. 

A simpler solution is to cascade two of the third order 
sections designed above. This cascaded design (Figure 10) 
works equally well for most applications. 

Figure 1 1 (a-d) shows the performance of this cascaded filter 
design. Note that the phase linearity and THD + N are still 
excellent using this approach. 

REFERENCES 

(1) R. Downs, "DSP Oversampling to Quiet Noise," EE 
Times, pg. 68, 8 August 1988. 

(2) R. Downs, "High Speed A/D Converter Lets Users Reap 
Benefits of Oversampling," Burr-Brown Update, Vol. XIV, 
No. 2, pg. 3, May 1988. 

(3) R. Downs, "Unique Topology Makes Simple, Low- 
Distortion Antialiasing Filters," to be published. 

(4) S.K. Mitra, Analysis and Synthesis of Linear Active 
Networks, John Wiley & Sons, Inc., New York, pg. 494, 
1969. 

(5) R. Downs, "Unique Topology Makes Simple, Low- 
Distortion Antialiasing Filters," to be published. 

(6) L.P. Huelsman, P.E. Allen, Introduction to the Theory 
and Design of Active Filters, McGraw-Hill, New York, 1980. 

(7) Ibid. 



40 
30 
20 
10 

-10 
-20 
-30 
^10 
-50 
-60 
-70 



20 



AMPLITUDE AND PHASE RESPONSE 
OF FILTER CIRCUIT IN FIGURE 6 



Amplitude 



100 



Phase 



90 ( 

C 

o i 

o 

— 90 
— 1 80 
-270 
-360 



1k 10k 
Frequency (Hz) 



100k 200k 



1 

0.8 
0.6 
0.4 
0.2 


-0.2 
-0.4 
-0.6 
-0.8 
-1 



20 



PASSBAND RESPONSE DETAIL 
OF FILTER CIRCUIT IN FIGURE 6 









































































































































































































t 


m 


jlitud 


e 








































































N 




































Ph 


a: 


e 



































































































































































100 



1k 10k 
Frequency (Hz) 



100k 200k 



(a) 



AMPLITUDE AND DEVIATION FROM LINEAR PHASE 
FOR FILTER IN FIGURE 6 



40 

20 




m 

CD 

I -40 
to 

<D 

K H50 
-80 



-100 



20 



Amplitude 



Phase 



.040 _ 

to 
9 
a> 

.020 o> 
S- 

U CO 

n 

-.020 f 
-.040 



100 



1k 10k 
Frequency (Hz) 



100k 200k 



Note phase scale— deviation from linear phase in critical 1 kHz-20kHz region 
is well within 0.1°. 

(c) 



TOTAL HARMONIC DISTORTION + NOISE 
OF FILTER CIRCUIT IN FIGURE 6 vs FREQUENCY 



-40 
-5 
-60 

I _7 ° 
^ -80 
Q 

jE -90 
-100 
-110 
-120 



20 



100 



1k 

Frequency (Hz) 



10k 20k 



NOTE: Referred to 6Vp-p full-scale signal typical of most digital audio 



(d) 



FIGURE 7. Performance Details of Figure 6 Circuit. 




40 
30 
20 
10 

-10 
-20 
-30 
-40 
-50 
-60 
-70 































































































































A 


T 


all 


ude~ 












































































\ 






















































































































'h 


a 


Si 












I 


























-F 


> 


•> 


\ 














































\ 





















































20 



100 



1k 10k 
Frequency (Hz) 



90 "J 

o I 

a 

-90 
-180 
-270 
-360 



100k 200k 



FIGURE 9. Amplitude (solid line) and Phase (dotted line) Re- 
sponse of Filter Circuit in Figure 8. (Note flattening 
of stopband response near 150kHz due to inadequate 
GBW of operational amplifiers used.) 




FIGURE 10. Sixth Order Linear-Phase Filter Made by Cascading Two Third Order Filters. 



AMPLITUDfc AND HHAijfc Htaruisac 
OF FILTER CIRCUIT IN FIGURE 10 



40 
30 
20 
10 


-10 
-20 
-30 
-AO 
-50 
-60 
-70 



Amplitude 



Phase 



90 "J 

U 

1 
a 

-90 
-180 
-270 
-360 



20 100 1k 10k 100k 200k 

Frequency (Hz) 

(a) 



AMPLTIUDE AND DEVIATION FROM LINEAR PHASE 
FOR FILTER IN FIGURE 10 



40 
20 




ffl 



-40 
-60 
-80 
-100 



"A 



Amplitude 



Phase 



.040 „ 

CD 
<D 

.020 o> 



CO 





-.020 ' 

-.040 

-.060 



CD 



20 



100 



1k 10k 
Frequency (Hz) 



100k 200k 



Note phase scale— deviation from linear phase in critical 1 kHz-20kHz region 
is well within 0.1°. 

(c) 



1 

0.8 
0.6 
0.4 
0.2 


-0.2 
-0.4 
-0.6 
-0.8 
-1 



20 



-40 
-5 
-60 

I _7 ° 
+ -80 

g 

X -90 
-100 
-110 



-120 



OF FILTER CIRCUIT IN FIGURE 10 



Phase 




-360 



100k 200k 



100 1k 10k 

Frequency (Hz) 

(b) 



TOTAL HARMONIC DISTORTION + NOISE 
FOR FILTER CIRCUIT IN FIGURE 10 vs FREQUENCY 



20 



100 



1k 

Frequency (Hz) 



10k 20k 



NOTE: Referred to 6Vp-p full-scale signal typical of most digital audio 
converters. 

(d) 



FIGURE 11. Performance Details of Figure 10 Circuit. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR -BROWN 

IMMI 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 1 1400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



MFB LOW-PASS FILTER DESIGN PROGRAM 

By Bruce Trump and R. Mark Stitt (602) 746-7445 



Although low-pass filters are vital in modern electronics, 
their design and verification can be tedious and time con- 
suming. The Burr-Brown FilterPro™ program, FILTER2, 
makes it easy to design low-pass active filters. The program 
is intended to aid in the design of low-pass filters imple- 
mented with the Multiple Feedback (MFB) topology. Be- 
cause there are instances where the Sallen-Key filter topol- 
ogy is a better choice, the program also supports Sallen-Key 
low-pass filter design. 

An ideal low-pass filter would completely eliminate signals 
above the cutoff frequency, and perfectly pass signals below 
cutoff (in the pass-band). In real filters, various trade-offs 
are made in an attempt to approximate the ideal. Some filter 
types are optimized for gain flatness in the pass-band, some 
trade-off gain variation (ripple) in the pass-band for steeper 
roll-off, still others trade-off both flatness and rate of roll-off 
in favor of pulse-response fidelity. FILTER2 supports the 
three most commonly used all-pole filter types: Butterworth, 
Chebyshev, and Bessel. 

Butterworth (maximally flat magnitude). This filter has the 
flattest possible pass-band magnitude response. Attenuation 
is -3dB at the design cutoff frequency. Attenuation above 
the cutoff frequency is a moderately steep -20dB/decade/ 
pole. The pulse response of the Butterworth filter has mod- 
erate overshoot and ringing. 



FILTER RESPONSE vs FREQUENCY 



+10 



CD 

5 -10 

CD 
O) 

1-20 

3 

K 

B -30 



-40 



-50 
fc/100 





















































































Rif 


>pl 


e 






































4 


-Pi 


)le( 
3dB 


Jhebys 


lev 
























Ripple 
































































































































































X 







































U10 



f,- 



10f n 



Normalized Frequency 



FIGURE 1A. Response vs Frequency of Even-Order 
(4-pole), 3dB Ripple Chebyshev Filter Show- 
ing Cutoff at OdB. 



Chebyshev (equal ripple magnitude). (Also transliterated 
Tschebychev, Tschebyscheff or Tchevysheff.) This filter 
type has steeper attenuation above the cutoff frequency than 
Butterworth. This advantage comes at the penalty of ampli- 
tude variation (ripple) in the pass-band. Unlike Butterworth 
and Bessel responses, which have 3dB attenuation at the 
cutoff frequency, Chebyshev cutoff frequency is defined as 
the frequency at which the response falls below the ripple 
band. For even-order filters, all ripple is above the OdB-gain 
DC response, so cutoff is at OdB — see Figure 1 A. For odd- 
order filters, all ripple is below the OdB-gain DC response, 
so cutoff is at -(ripple) dB — see Figure IB. For a given 
number of poles, a steeper cutoff can be achieved by allow- 
ing more pass-band ripple. The Chebyshev has even more 
ringing in its pulse response than the Butterworth. 

Bessel (maximally flat time delay). (Also called Thomson.) 
Due to its linear phase response, this filter has excellent 
pulse response (minimal overshoot and ringing). For a given 
number of poles, its magnitude response is not as flat, nor is 
its attenuation beyond the -3dB cutoff frequency as steep as 
the Butterworth. It takes a higher-order Bessel filter to give 
a magnitude response which approaches that of a given 
Butterworth filter, but the pulse response fidelity of the 
Bessel filter may make the added complexity worthwhile. 



FILTER RESPONSE vs FREQUENCY 





+10 







m 






-10 


CD 




CO 




>spor 


-20 






£ 


-30 


il 






-40 




-50 



















































































I 






































s 
























































Ripple 








5 


-F 




3 


e 




C 


hebys 


lev 


































dB Ripple 

















































































































































































































































































































f c /ioo vio f c 

Normalized Frequency 



10f n 



FIGURE IB. Response vs Frequency of Odd-Order (5- 
pole), 3dB Ripple Chebyshev Filter Showing 
Cutoff at -3dB. 



'1991 Burr-Brown Corporation 



AB-034B 



Printed in U.S.A. November. 1991 



v, N o- 




-ov 



v v 

Optional Buffer Real Pole Section 




v 

Optional Buffer 



Complex 
Pole-Pair 
Section A 



FIGURE 2. Real Pole Section (Unity-Gain, First-Order 
Butterworth; f_ 3dB = 1/2 • n • • C,). 



FIGURE 3. Second-Order Low-Pass Filter. 



v, N o- 



Optional Buffer 




v 

Real Pole Section 



Complex 
Pole-Pair 
Section A 



FIGURE 4. Third-Order Low-Pass Filter. 




Complex 
Pole-Pair 
Section A 



Complex 
Pole-Pair 
Section N 



v 

Optional Buffer 



FIGURE 5. Even-Order Low-Pass Filter Using Cascaded Complex Pole-Pair Sections. 



v IN o- 




v v 

Optional Buffer Real Pole Section 



Complex 
Pole- Pair 
Section A 



Complex 
Pole- Pair 
Section N 



FIGURE 6. Odd-Order Low-Pass Filter Using Cascaded Complex Pole-Pair Sections Plus One Real-Pole Section. 



Butterworth 

Advantages 



Disadvantages 

Chebyshev 

Advantages 

Disadvantages 



Advantages 



Disadvantages 



Maximally flat magnitude response in the 
pass-band. Good all-around performance. 
Pulse response better than Chebyshev. Rate 
of attenuation better than Bessel. 

Some overshoot and ringing in step re- 
sponse. 

Better attenuation beyond the pass-band 
than Butterworth. 

Ripple in pass-band. Considerable ringing 
in step response. 



Best step response — very little overshoot 
or ringing. 

Slower rate of attenuation beyond the pass- 
band than Butterworth. 



CIRCUIT IMPLEMENTATION 

Even-order filters designed with this program consist of 
cascaded sections of complex pole-pairs. Odd-order filters 
contain an additional real-pole section. Figures 2 through 6 
show the recommended cascading arrangement. The pro- 
gram automatically places lower Q stages ahead of higher Q 
stages to prevent op amp output saturation due to gain peaking. 
The program can be used to design filters up to 8th order. 



FILTER ORDER 


FIGURE 


1 pole 


Figure 2 


2 poles 


Figure 3 


3 poles 


Figure 4 


4 or more poles (even order) 


Figure 5 


5 or more poles (odd order) 


Figure 6 



TABLE L Filter Circuit vs Filter Order. 

COMPLEX POLE-PAIR CIRCUIT 

The choice of a complex pole-pair circuit depends on perfor- 
mance requirements. FTLTER2 supports the two most com- 
monly used op amp pole-pair circuit topologies: 

• Multiple Feedback (MFB) — shown in Figure 7. 

• Sallen-Key — shown in Figures 8 and 9. 

The MFB topology (sometimes called Infinite Gain or Rauch) 
is often preferred due to assured low sensitivity to compo- 
nent variations — see sensitivity section. There are instances, 
however, where the Sallen-Key topology is a better choice. 

As a rule of thumb, the Sallen-Key topology is better if: 

1) Gain accuracy is important, AND 

2) A unity-gain filter is used, AND 

3) Pole-pair Q is low (e.g. Q < 3) 



R 2 



c 2 




FIGURE 7. MFB Complex Pole-Pair Section. 
(Gain = -R2/R1) 




FIGURE 8. Unity-Gain Sallen-Key Complex Pole-Pair 
Section. (Gain =1) 




FIGURE 9. Sallen-Key Complex Pole-Pair Section. 
(Gain = 1 + R^) 

At unity-gain, the Sallen-Key topology inherently has excel- 
lent gain accuracy. This is because the op amp is used as a 
unity-gain buffer. With the MFB topology, gain is deter- 
mined by the R2/R1 resistor ratio. The unity-gain Sallen-Key 
topology also requires fewer components — two resistors vs 
three for MFB. 

The Sallen-Key topology may also be preferable for high-Q 
high frequency filter sections. In these sections the value 
required for Ci in a MFB design can be quite low for 
reasonable resistor values. Low capacitor values can result 
in significant errors due to parasitic capacitances. 



The best filter design may be a combination of MFB and 
Sallen-Key sections. 

Use the appropriate circuits along with component values 
generated by the FILTER2 program to build your filter 
design. 

USING THE FILTERPRO™ PROGRAM 

With each data entry, the program automatically calculates 
filter performance and values for all filter components. This 
allows you to use a "what if spreadsheet-type design 
approach. For example, you can quickly determine, by trial 
and error, how many poles are needed for a given roll-off. 

GETTING STARTED 

The first time you use the program, you may want to follow 
these steps. 

Type FILTER2 <ENTER> to start the program. 

At this point, you have already designed a 3-pole, 1kHz 
Butterworth filter. Component values are shown on the 
display screen. For a different filter design, use the arrow 
keys to move the cursor to the menu selection desired. 

Start at the top of the menu and work your way down. On- 
screen prompts, to the left of the menu selections, will guide 
you in program use. Refer to this bulletin for more detail, if 
needed. 

1) Choose pole-pair Circuit: MFB or Sallen-Key 

2) Select Filter type: Butterworth 

Chebyshev 
Bessel 

3) For Chebyshev filter type, enter Ripple: >0dB to 4dB 

4) Enter Number of poles: 1 to 8 

5) Enter filter Cutoff frequency: (Hz) 
The following steps are optional: 

6) If you want to view the gain/phase response of the 
current filter design at a particular frequency, enter the 
frequency of interest on the Response @ fx line. The 
gain/phase information can be viewed on the fn, Q, 
Response display window — see step 11. 

7) If you want to change the resistor scaling, enter a value 
on the Scale Resistors line. 

8) If you want to change the gain of a section, press 
<ENTER> on the Gain Entry line. Default value for 
gain is 1.0V/V in each section. 

9) If you want to enter your own capacitor values, press 
<ENTER> on the Capacitor Menu line. 

10) If you want to design with standard 1% resistors instead 
of exact resistors, press <ENTER> on the Resistors 
line. 



11) To change the display screen press <ENTER> on the 
Display line. Available display screens are: Component 
values; fn, Q, Response; Sensitivities. 

TO RETURN TO DOS 

To exit the program and return to DOS, press <F1>. 
USING THE PLOT FEATURE 

A Plot feature allows you to view graphical results of filter 
gain and phase vs frequency. This feature is useful for 
comparing filter types. 

To view a plot of the current filter design, press <F2>. 

GRAPHIC DISPLAY COMMANDS 

While viewing the graphic display, several commands can 
be used to compare filter responses: 

S — Saves the plot of the current design for future recall. 

R — Recalls the Saved plot and plots it along with the current 
design. 

P — Recalls the Previous plot of the last design plotted from 
the main program (by pressing <F2>) and plots it along with 
the current design. You can recall the Previous design and 
the Saved design to plot all three together. 

C — Clears the display and replots only the current design. 

GRAPHIC DISPLAY CURSOR CONTROL 

While viewing the graphics display you can also use the left/ 
right arrow keys to move a cursor and view gain and phase 
for plotted filter responses. The gain/phase of the current 
design is always displayed. In addition, the gain/phase of the 
Recalled or Previous design can be viewed by pressing R or 
P. 

TO PRINT RESULTS 

To print results press <F3>. All three display screens will 
automatically be printed. 

SENSITIVITY 

Sensitivity is the measure of the vulnerability of a filter's 
performance to changes in component values. The important 
filter parameters to consider are natural frequency (f n ) and Q. 

f n SENSITIVITY FOR BOTH 
MFB AND SALLEN-KEY 

Sensitivity of f„ to resistor, capacitor, and amplifier gain 
variations is always low for both the Sallen-Key and MFB 
filter topologies. 



155 



S^=Sc=±0.5%/% 

Sk=0 

Where: 

S f R , S ( c , S ( K = Sensitivity of f n to resistor, 

capacitor, and gain variations 

(%/%) 



Q SENSITIVITY 

For the MFB topology, sensitivities to Q are also always 
low, but sensitivities for the Sallen-Key topology can be 
quite high — exceeding 2 • K • Q 2 . At unity gain, the Sallen- 
Key Q sensitivity to resistor and capacitor variations will 
always be low. Unfortunately, however, the sensitivity of 
the unity-gain Sallen-Key pole-pair to op amp gain can be 
high. 

Q Sensitivity for MFB Pole-Pair 

S£ = ±0.5%/% 

S Q _ + R 2 ~ R 3 ~ K ' R 3 (MFB complex 
R ~ 2(R 2 + R 3 + K • R 3 ) pole-pair) 

S Q = K * R 3 (MFB complex 

K R 2 + R 3 + K • R 3 pole-pair) 

Notice, by inspection: S^ is always less than ±0.5%/%, 
and S^ is always less than 1.0%/%. 

Q Sensitivity for Gain = 1 Sallen-Key Pole-Pair 

S£ = ±0.5%/% 

S Q = ± R ' ~ R 2 (Sallen-Key 

2(R, + R 2 ) complex pole-pair) 

So, S^ is always less than 0.5%/%. 

Q 2 < S^ < 2 • Q 2 (Sallen-Key complex pole-pair) 

Where: 

S^, S^, S^ = Sensitivity of f and Q to resistor, 
capacitor, and gain variations 
(%/%) 
K = Op amp gain (V/V) 

Figure 7 circuit, K = R 2 /Rj 
Figure 8 circuit, K = 1 .0 
Figure 9 circuit, K = 1 + R 4 /R 3 

NOTE: FilterPro™ always selects component values so 
unity-gain Sallen-Key S£ will be closer to Q 2 than to 2 • Q 2 . 

However, FILTER2 will allow you to design Sallen-Key 
pole-pairs with high sensitivities (high Qs and GAIN » 1). 
You must make sure that sensitivities to component varia- 
tions do not make these designs impractical. A feature in the 
Display menu allows you to view the f„ and Q sensitivity of 
filter sections to resistor and capacitor variations. 



USING THE SENSITIVITY DISPLAY FEATURE 

To use the Sensitivity display option, move the cursor to the 
Display menu, press <ENTER>, move the cursor to the 
Sensitivity selection, and press <ENTER> again. The dis- 
play shows sensitivity of f n and Q to each component for 
each filter section. The format is S f ; S Q . 

Rather than displaying the derivative with respect to compo- 
nent variations, the program calculates f n and Q change for 
a 1% change in component values. This gives a more 
realistic sensitivity value for real-world variations. 

USING THE SCALE RESISTORS MENU OPTION 

The Scale Resistors option allows you to scale the com- 
puter-selected resistor values to match the application. Move 
the cursor to the Scale Resistors menu selection and enter 
your seed resistor value. The default value of 10k£2 is 
suggested for most applications. 

Higher resistor values, e.g. lOOkQ, can be used with FET- 
input op amps. At temperatures below about 70°C, DC 
errors and excess noise due to op amp input bias current will 
be small. Remember, however, that noise due to the resistors 
will be increased by where n is the resistor increase 
multiplier. 

Lower resistor values, e.g. 500£2, are a better match for high- 
frequency filters using the OPA620 or OPA621 op amps. 

CAPACITOR VALUES 

Compared to resistors, capacitors with tight tolerances are 
more difficult to obtain and can be much more expensive. 
The Capacitor menu option allows you to enter actual 
measured capacitor values. In this way, an accurate filter 
response can be achieved with relatively inexpensive com- 
ponents. 

USING THE CAPACITOR MENU OPTION 

To use the Capacitor menu option, move the cursor to the 
Capacitor menu selection and press <ENTER>. Move the 
cursor to any capacitor and enter your value. Prompts on the 
left of the screen advise min/max capacitor entry limits. 
With each capacitor entry, the program will select exact or 
closest standard 1% resistor values as before. 

COMPENSATE FOR OP AMP 

INPUT CAPACITANCE— SALLEN-KEY ONLY 

If the common-mode input capacitance of the op amp used 
in a Sallen-Key filter section is more than approximately 
C[/400 (0.25% of C[), it must be considered for accurate 
filter response. You can use the Capacitor menu option to 
compensate for op amp input capacitance by simply adding 
the value of the op amp common-mode input capacitance to 
the actual value of C,. The program then automatically 



recalculates the exact or closest 1% resistor values for 
accurate filter response. No compensation for op amp input 
capacitance is required with MFB designs. 

CAPACITOR SELECTION 

Capacitor selection is very important for a high-performance 
filter. Capacitor behavior can vary significantly from ideal, 
introducing series resistance and inductance which limit Q. 
Also, nonlinearity of capacitance vs voltage causes distortion. 

Common ceramic capacitors with high dielectric constants, 
such as "high-K" types, can cause errors in filter circuits. 
Recommended capacitor types are: NPO ceramic, silver 
mica, metallized polycarbonate; and, for temperatures up to 
85°C, polypropylene or polystyrene. 

OP AMP SELECTION 

It is important to choose an op amp that can provide the 
necessary DC precision, noise, distortion, and speed. 

OP AMP BANDWIDTH 

In a low-pass filter section, maximum gain peaking is very 
nearly equal to Q at f n (the section's natural frequency). So, 
as a rule of thumb: 

For an MFB section: Op amp bandwidth should be at least 

100 • GAIN • f„. 
High-Q Sallen-Key sections require higher op amp band- 
width. 

For a Sallen-Key section: For Q > 1, op amp gain- 
bandwidth should be at least 
100 • GAIN • Q 3 • f„. 
For Q < 1, op amp gain- 
bandwidth should be at least 
100 • GAIN • f n . 

For a real-pole section: Op amp bandwidth should be at 

least 50 • f n . 

Although Q is formally defined only for complex poles, it is 
convenient to use a Q of 0.5 for calculating the op amp gain 
required in a real-pole section. 

For example, a unity-gain 20kHz 5-pole, 3dB ripple 
Chebyshev MFB filter with a 2nd pole-pair f n of 19.35kHz 
and a Q of 8.82 needs an op amp with unity gain bandwidth 
of at least 17MHz. On the other hand, a 5-pole Butterworth 
MFB filter, with a worst case Q of 1 .62 needs only a 3.2MHz 
op amp. The same 5-pole Butterworth filter implemented 
with a Sallen-Key topology would require a 8.5MHz op amp 
in the high-Q section. 

USING THE f n AND Q DISPLAY OPTION 

To aid in selection of the op amp, a feature in the Display 
menu section allows you to view pole-pair section f n and Q. 

To use this feature move the cursor to the Display menu, 
press <ENTER>, move the cursor to the f „ & Q selection, 



and press <ENTER> again. The f n and Q information is also 
useful when trouble-shooting filters by comparing expected 
to actual response of individual filter sections. 

OP AMP SLEW RATE 

For adequate full-power response, the slew rate of the op amp 
must be greater than jc • V p-p • filter bandwidth. For 
example, a 100kHz filter with 20Vp-p output requires an op 
amp slew rate of at least 6.3V/(is. Burr-Brown offers an excel- 
lent selection of op amps which can be used for high perfor- 
mance active filters. The guide on P-7 lists some good choices. 

THE UAF42 UNIVERSAL ACTIVE FILTER 

For other filter designs, consider the Burr-Brown UAF42 
Universal Active Filter. It can easily be configured for a 
wide variety of low-pass, high-pass, band-pass, or band- 
reject (notch) filters. It uses the classical state-variable 
architecture with an inverting amplifier and two integrators 
to form a pole-pair. The integrators include on-chip lOOOpF, 
±0.5% capacitors. This solves one of the most difficult 
problems in active filter implementation — obtaining tight 
tolerance, low-loss capacitors at reasonable cost. 

Simple design procedures for the UAF42 allow implemen- 
tation of Butterworth, Chebyshev, Bessel, and other types of 
filters. An extra FET-input op amp in the UAF42 can be used 
to form additional stages or special filter types such as Inverse 
Chebyshev. The UAF42 is available in a standard 14-pin DIP. 
For more information, request the Burr-Brown Product Data 
Sheet PDS-1070 and Application Bulletin AB-035. 

EXAMPLES OF MEASURED 
MFB FILTER RESPONSE 

Figures 10 and 11 show actual measured magnitude re- 
sponse plots for 5th-order 20kHz Butterworth, 3dB 
Chebyshev and Bessel filters designed with the program. 
The op amp used in all filters was the OPA627. As can be 
seen in Figure 10, the initial roll-off of the Chebyshev filter 
is fastest and the roll-off of the Bessel filter is the slowest. 
However, each of the 5th-order filters ultimately rolls off at 
-N • 20dB/decade, where N is the filter order (-100dB/ 
decade for a 5-pole filter). 

The oscilloscope photographs (Figures 12-14) show the step 
response for each filter. As expected, the Chebyshev filter 
has the most ringing, while the Bessel has the least. Figure 
15 shows distortion plots vs frequency for the three filters. 

See Application Bulletin AB-017 for measured Sallen-Key 
filter performance of the same three designs. 



T A - 25°C, V s - ±15V, specifications typ, unless otherwise noted, min/max specifications are tor mgn-graoe moaei. 





BW 


fpr m 


SR 


Vos 


Vos/dT 


NOISE 




OP AMP 


typ 


typ 


typ 


max 


max 


at 10kHz 


Ccm (3) 


imnci 

MUUEL 


\fnnz) 


(KHZ) 










(Pn 


OPA177 
Urn I / / 


U.D 


o 
a 




1 n 
1 U 


-*-n 1 
±U.l 


a 
O 


4 
1 




o 
o 




1 o 




xu.o 


7 


4 


nPA9in7 Hual (2) 

\jrt\tL audi 


A C 




1 Q 


con 


ID 


Q 
O 




nPAfifl9 (2) 


O 


500 


oo 


C9U 


■4-0 

33! 




O 

o 


OPA404 quad (2) 


6 


500 


35 


1000 


±3 tVD 


12 


3 


OPA627 <2) 


16 


875 


55 


100 


±0.8 


4.5 


7 


OPA620 (V s = ±5V) 


300 


16MHz(5Vp-p) 


250 


500 


±8 typ 


2.3 @1 MHz 


1 



NOTES: (1 ) Unless otherwise noted, FPR is full power response at 20Vp-p as calculated from slew rate. (2) These op amps have FET inputs. (3) Common-mode input 
capacitance. 



10 


-10 
-20 
-30 
-40 
-50 
-60 
-70 
-80 
-90 























































E 


ie; 


s 


)l 










































































Bi 


tlf 


r\ 


/orth- 




















































3d 


3C 


ie 




shev- 







































































































200 1k 10k 

Frequency (Hz) 



200k 



FIGURE 10. Gain vs Frequency for Fifth-Order 20kHz 
Butterworth, Chebyshev, and Bessel Unity- 
Gain MFB Low-Pass Filters, Showing Over- 
all Filter Response. 



+3 

-3 


































































































-6 


























E 


essel — 






-9 
■12 
-15 
-18 
-21 
-24 

n*7 






















































B 


ut 


ter 


worth 






















































3 


iB 


C 


h 




'shev — > 







































































400 



1k 



10k 



20k 



40k 



Frequency (Hz) 



FIGURE 11. Gain vs Frequency for Fifth-Order 20kHz 
Butterworth, Chebyshev, and Bessel Unity- 
Gain MFB Low-Pass Filters, Showing Transi- 
tion-Band Detail. 




FIGURE 12. Step Response of Fifth-Order 20kHz 
Butterworth Low-Pass MFB Filter. 




FIGURE 14. Step Response of Fifth-Order 20kHz Bessel 
Low-Pass MFB Filter. 




FIGURE 13. Step Response of Fifth-Order 20kHz 
Chebyshev Low-Pass MFB Filter. 



FILTER THD, 20kHz, 5 POLE 



0.1 



0.01 



0.001 



10 




10 2 10 3 10" 

Frequency (Hz) 



FIGURE 15. Measured Distortion for the Three 20kHz MFB 
Low-Pass Filters. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR -BROWN® 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 

FILTER DESIGN PROGRAM FOR 
THE UAF42 UNIVERSAL ACTIVE FILTER 



159 



By Johnnie Molina and R. Mark Stitt (602) 746-7592 



Although active filters are vital in modern electronics, their 
design and verification can be tedious and time consuming. 
To aid in the design of active filters, Burr-Brown provides 
a series of FilterPro™ computer-aided design programs. 
Using the FILTER42 program and the UAF42 it is easy to 
design and implement all kinds of active filters. The UAF42 
is a monolithic IC which contains the op amps, matched 
resistors, and precision capacitors needed for a state-variable 
filter pole-pair. A fourth, uncommitted precision op amp is 
also included on the die. 

Filters implemented with the UAF42 are time-continuous, 
free from the switching noise and aliasing problems of 
switched-capacitor filters. Other advantages of the state- 
variable topology include low sensitivity of filter parameters 
to external component values and simultaneous low-pass, 
high-pass, and band-pass outputs. Simple two-pole filters 
can be made with a UAF42 and two external resistors — see 
Figure I. 

The DOS-compatible program guides you through the de- 
sign process and automatically calculates component values. 
Low-pass, high-pass, band-pass, and band-reject (or notch) 
filters can be designed. 

Active filters are designed to approximate an ideal filter 
response. For example, an ideal low-pass filter completely 



eliminates signals above the cutoff frequency (in the stop- 
band), and perfectly passes signals below it (in the pass- 
band). In real filters, various trade-offs are made in an 
attempt to approximate the ideal. Some filter types are 
optimized for gain flatness in the pass-band, some trade-off 
gain variation or ripple in the pass-band for a steeper rate of 
attenuation between the pass-band and stop-band (in the 
transition-band), still others trade-off both flatness and rate 
of roll-off in favor of pulse-response fidelity. FILTER42 
supports the three most commonly used all-pole filter types: 
Butterworth, Chebyshev, and Bessel. The less familiar In- 
verse Chebyshev is also supported. If a two-pole band-pass 
or notch filter is selected, the program defaults to a resonant- 
circuit response. 

Butterworth (maximally flat magnitude). This filter has the 
flattest possible pass-band magnitude response. Attenuation 
is -3dB at the design cutoff frequency. Attenuation beyond 
the cutoff frequency is a moderately steep -20dB/decade/ 
pole. The pulse response of the Butterworth filter has mod- 
erate overshoot and ringing. 

Chebyshev (equal ripple magnitude). (Other transliterations 
of the Russian MeSuuieB are Tschebychev, Tschebyscheff or 
Tchevysheff). This filter response has steeper initial rate of 
attenuation beyond the cutoff frequency than Butterworth. 



15.8kn 



13 



"2 

50kQ 



50kQ 

vw- 




A, 



15.8k£2 

i — vW — I 



-m- 

50kQ 

c, 



1000pF 



R4 

50kQ 




14 



1000pF 



NOTE: A UAF42 and two external resistors make a unity-gain, two-pole, 1 .25dB ripple 
Chebyshev low-pass filter. With the resistor values shown, cutoff frequency is 1 0kHz. 




11 



UAF42 




-ov„ 



CO 

i- 

J? 
E 



a> 

"5 
m 

c 
o 

CO 

o 

Q. 
Q. 
< 



FIGURE 1. Two-Pole Low-Pass Filter Using UAF42. 



S I991 Burr-Brown Corporation 



AB-035C 



Printed in U.S.A. May, 1992 



FILTER RESPONSE vs FREQUENCY 



+10 


S 

2. -10 

9 

-20 
<r 

| -30 

5. 

-to 



-50 
f c /100 























1 




























































' t 


Ri, 


>pl 


e 
























i 














4 


-P< 


)le( 


ihebysl 


lev 






















3dB Ripple 


































































































P 





































































































fc/10 f c 
Normalized Frequency 



10f c 



FIGURE 2A. Response vs Frequency for Even-Order (4- 
pole) 3dB Ripple Chebyshev Low-Pass Filter 
Showing Cutoff at OdB. 



FILTER RESPONSE vs FREQUENCY 



+10 



m 

S -10 

o 

m 

1-20 

B 

EE 

S -30 
iZ 

-40 



-50 
f c /100 











































































il 





| 
























































































i: 


Rp 


Me 








5 


-F 


ole 


C 


hebys 


lev 


































3dB Ripple 





































































































































































































































































































fc/10 <c 
Normalized Frequency 



10f c 



FIGURE 2B. Response vs Frequency for Odd-Order (5- 
pole) 3dB Ripple Chebyshev Low-Pass Filter 
Showing Cutoff at -3dB. 



This advantage comes at the penalty of amplitude variation 
(ripple) in the pass-band. Unlike Butterworth and Bessel 
responses, which have 3dB attenuation at the cutoff fre- 
quency, Chebyshev cutoff frequency is defined as the fre- 
quency at which the response falls below the ripple band. 
For even-order filters, all ripple is above the OdB-normal- 
ized passband gain response, so cutoff is at OdB (see Figure 
2A). For odd-order filters, all ripple is below the OdB- 
normalized passband gain response, so cutoff is at -(ripple) 
dB (see Figure 2B). For a given number of poles, a steeper 
cutoff can be achieved by allowing more pass-band ripple. 
The Chebyshev has more ringing in its pulse response than 
the Butterworth — especially for high-ripple designs. 

Inverse Chebyshev (equal minima of attenuation in the stop 
band). As its name implies, this filter type is cousin to the 



FILTER RESPONSE vs FREQUENCY 



ra 

E" -60 

o 

z 

-80 
-100 













































































































s 


s 






















































s 


I 












































































\ 


















































i 


m 










































































































































** 
































-fj 


TO 


PC 


A 















































































































































f c /10 f c 10f c 100f c 

Normalized Frequency 



FIGURE 3. Response vs Frequency for 5-pole, -60dB 
Stop-Band, Inverse Chebyshev Low-Pass Filter 
Showing Cutoff at -60dB. 



Chebyshev. The difference is that the ripple of the Inverse 
Chebyshev filter is confined to the stop-band. This filter type 
has a steep rate of roll-off and a flat magnitude response in 
the pass-band. Cutoff of the Inverse Chebyshev is defined as 
the frequency where the response first enters the specified 
stop-band — see Figure 3. Step response of the Inverse 
Chebyshev is similar to the Butterworth. 

Bessel (maximally flat time delay), also called Thomson. 
Due to its linear phase response, this filter has excellent 
pulse response (minimal overshoot and ringing). For a given 
number of poles, its magnitude response is not as flat, nor is 
its initial rate of attenuation beyond the -3dB cutoff fre- 
quency as steep as the Butterworth. It takes a higher-order 
Bessel filter to give a magnitude response similar to a given 
Butterworth filter, but the pulse response fidelity of the 
Bessel filter may make the added complexity worthwhile. 

Tuned Circuit (resonant or tuned-circuit response). If a 
two-pole band-pass or band-reject (notch) filter is selected, 
the program defaults to a tuned circuit response. When band- 
pass response is selected, the filter design approximates the 
response of a series-connected LC circuit as shown in Figure 
4A. When a two-pole band-reject (notch) response is se- 
lected, filter design approximates the response of a parallel- 
connected LC circuit as shown in Figure 4B. 

CIRCUIT IMPLEMENTATION 

In general, filters designed by this program are implemented 
with cascaded filter subcircuits. Subcircuits either have a 
two-pole (complex pole-pair) response or a single real-pole 
response. The program automatically selects the subcircuits 
required based on function and performance. A program 
option allows you to override the automatic topology selec- 
tion routine to specify either an inverting or noninverting 
pole-pair configuration. 



suocircuu as snown 111 nguic j. iviutt u«upM mms 
consist of two or more cascaded subcircuits as shown in 
Figure 6. Even-order filters are implemented entirely with 
UAF42 pole-pair sections and normally require no external 
capacitors. Odd-order filters additionally require one real 
pole section which can be implemented with the fourth 
uncommitted op amp in the UAF42, an external resistor, and 
an external capacitor. The program can be used to design 
filters up to tenth order. 

The program guides you through the filter design and gen- 
erates component values and a block diagram describing the 
filter circuit. The Filter Block Diagram program output 
shows the subcircuits needed to implement the filter design 
labeled by type and connected in the recommended order. 
The Filter Component Values program output shows the 
values of all external components needed to implement the 
filter. 



SUMMARY OF FILTER TYPES 


Butterworth 




Advantages: 


Maximally flat magnitude 




response in the pass-band. 




Good all-around performance. 




Pulse response better than 




Chebyshev. 




Rate of attenuation better than 




Bessel. 


Disadvantages: 


Some overshoot and ringing in 




step response. 


Chebyshev 




Advantages: 


Better attenuation beyond the 




pass-band than Butterworth. 


Disadvantages: 


Ripple in pass-band. 




Considerably more ringing in 




step response than Butterworth. 


Inverse Chebyshev 


Advantages: 


Flat magnitude response in 




pass-band with steep rate of 




attenuation in transition-band. 


Disadvantages: 


Ripple in stop-band. 




Some overshoot and ringing in 




step response. 


Bessel 

Advantages: 


Best step response — very little 




overshoot or ringing. 


Disadvantages: 


Slower initial rate of attenua- 




tion beyond the pass-band than 




Butterworth. 



-ov 



1 A1 



FIGURE 4A. n = 2 Band-Pass Filter Using UAF42 (ap- 
proximates the response of a series-connected 
tuned L, C, R circuit). 




FIGURE 4B. n = 2 Band-Reject (Notch) Filter Using 
UAF42 (approximates the response of a par- 
allel-connected tuned L, C, R circuit). 



Subcircuit 1 



v IN o- 



(1) 



Out<*> 



-OV 



NOTES: 

(1 ) Subcircuit will be a complex pole-pair (PP1 through PP6) 
subcircuit specified on the UAF42 Filter Component Values and 
Filter Block Diagram program outputs. 

(2) HP Out, BP Out, LP Out, or Aux Out will be specified on the 
UAF42 Filter Block Diagram program output. 



FIGURE 5. Simple Filter Made with Single Complex Pole- 
Pair Subcircuit. 



Subcircuit 1 



Subcircuit N 



V,nO- 





(1) 


Out« 


In 


(D 


OutW t 









-ov 



NOTES: 

(1 ) Subcircuit will be a real-pole high-pass (HP), real-pole low-pass 
(LP), or complex pole-pair (PP1 through PP6) subcircuit specified 
on the UAF42 Filter Component Values and Filter Block Diagram 
program outputs. 

(2) If the subcircuit is a pole-pair section, HP Out, BP Out, LP Out, or 
Aux Out will be specified on the UAF42 Filter Block Diagram 
program output. 



FIGURE 6. Multiple-Stage Filter Made with Two or More 
Subcircuits. 



The program automatically places lower Q stages ahead of 
higher Q stages to prevent op amp output saturation due to 
gain peaking. Even so, peaking may limit input voltage to 
less than +10V (V s = +15V). The maximum input voltage 
for each filter design is shown on the filter block diagram. 
If the UAF42 is to be operated on reduced supplies, the 
maximum input voltage must be derated commensurately. 
To use the filter with higher input voltages, you can add an 
input attenuator. 

The program designs the simplest filter that provides the 
desired AC transfer function with a pass-band gain of 
1.0V/V. In some cases the program cannot make a unity- 
gain filter and the pass-band gain will be less than 1 .OV/V. 
In any case, overall filter gain is shown on the filter block 
diagram. If you want a different gain, you can add an 
additional stage for gain or attenuation as required. 

To build the filter, print-out the block diagram and compo- 
nent values. Consider one subcircuit at a time. Match the 
subcircuit type referenced on the component print-out to its 
corresponding circuit diagram — see the Filter Subcircuits 
section of this bulletin. 

The UAF42 Filter Component Values print-out has places to 
display every possible external component needed for any 
subcircuit. Not all of these components will be required for 
any specific filter design. When no value is shown for a 
component, omit the component. For example, the detailed 
schematic diagrams for complex pole-pair subcircuits show 
external capacitors in parallel with the lOOOpF capacitors in 
the UAF42. No external capacitors are required for filters 
above approximately 10Hz. 

After the subcircuits have been implemented, connect them 
in series in the order shown on the filter block diagram. 

FILTER SUBCIRCUITS 

Filter designs consist of cascaded complex pole-pair and 
real-pole subcircuits. Complex pole pair subcircuits are 
based on the UAF42 state-variable filter topology. Six varia- 
tions of this circuit can be used, PP1 through PP6. Real pole 
sections can be implemented with the auxiliary op amp in 
the UAF42. High-pass (HP) and low-pass (LP) real-pole 
sections can be used. The subcircuits are referenced with a 
two or three letter abbreviation on the UAF42 Filter Compo- 
nent Values and Filter Block Diagram program outputs. 
Descriptions of each subcircuit follow: 

POLE-PAIR (PP) SUBCIRCUITS 

In general, all complex pole-pair subcircuits use the UAF42 
in the state-variable configuration. The two filter parameters 
that must be set for the pole-pair are the filter Q and the 
natural frequency, f . External resistors are used to set these 
parameters. Two resistors, R F i and Rp2, must be used to set 
the pole-pair f . A third external resistor, R Q , is usually 
needed to set Q. 



At low frequencies, the value required for the frequency- 
setting resistors can be excessive. Resistor values above 
about 5MI2 can react with parasitic capacitance causing 
poor filter performance. When f Q is below 10Hz, external 
capacitors must be added to keep the value of R F1 and R^ 
below 5MQ . When f Q is in the range of about 10Hz to 32Hz, 
An external 5.49kQ resistor, R 2A . is added in parallel with 
the internal resistor, R 2 , to reduce R R and R^ by VlO and 
eliminate the need for external capacitors. At the other 
extreme, when f is above 10kHz, R 2A , is added in parallel 
with R 2 to improve stability. 

External filter gain-set resistors, Re, are always required 
when using an inverting pole-pair configuration or when 
using a noninverting configuration with Q < 0.57. 

PP1 (Noninverting pole-pair subcircuit using internal gain- 
set resistor, R 3 ) — See Figure 7. In the automatic topology 
selection mode, this configuration is used for all band-pass 
filter responses. This configuration allows the combination 
of unity pass-band gain and high Q (up to 400). Since no 
external gain-set resistor is required, external parts count is 
minimized. 

PP2 (Noninverting pole-pair subcircuit using an external 
gain-set resistor, Rg) — See Figure 8. This configuration is 
used when the pole-pair Q is less than 0.57. 

PP3 (Inverting pole-pair subcircuit) — See Figure 9A. In the 
automatic topology selection mode, this configuration is 
used for the all-pole low-pass and high-pass filter responses. 
This configuration requires an external gain-set resistor, Rq. 
With Rq = 50k£2, low-pass and high-pass gain are unity. 

PP4 (Noninverting pole-pair/zero subcircuit) — See Figure 

10. In addition to a complex pole-pair, this configuration 
produces a jco-axis zero (response null) by summing the low- 
pass and high-pass outputs using the auxiliary op amp, A 4 , 
in the UAF42. In the automatic topology selection mode, 
this configuration is used for all band-reject (notch) filter 
responses and Inverse Chebyshev filter types when 
Q > 0.57. This subcircuit option keeps external parts count 
low by using the internal gain-set resistor, R 3 . 

PP5 (Noninverting pole-pair/zero subcircuit) — See Figure 

11. In addition to a complex pole-pair, this configuration 
produces a jco-axis zero (response null) by summing the low- 
pass and high-pass outputs using the auxiliary op amp, At, 
in the UAF42. In the automatic topology selection mode, 
this configuration is used for all band-reject (notch) filter 
responses and Inverse Chebyshev filter types when 
Q < 0.57. This subcircuit option requires an external gain-set 
resistor, R G . 

PP6 (Inverting pole-pair/zero subcircuit) — See Figure 12. In 
addition to a complex pole-pair, this configuration produces 
a jco-axis zero (response null) by summing the low-pass and 
high-pass outputs using the auxiliary op amp, A 4 , in the 
UAF42. This subcircuit is only used when you override the 
automatic topology selection algorithm and specify the in- 
verting pole-pair topology. Then it is used for all band-reject 
(notch) filter responses and Inverse Chebyshev filter types. 



PP1 



12 



Q HP Out 



13 



R 2 



R 3 

sokn 




A, 



9 BP Out 
R F2 



50k£l 



1000pF 



R 4 
50kQ 




Q LP Out 



14 



C 2 
1000pF 

A3 




UAF42 



11 



163 



FIGURE 7. PP1 Noninverting Pole-Pair Subcircuit Using Internal Gain-Set Resistor R 3 . 



PP2 



12 



R 2A 



9 HP Out 
Rp, 



13 



R 2 
50kQ 




A, 



R4 

50k£l 



9 BP Out 
R F2 



R, 

50k« 

4 



1000pF 




9 LP Out 



Hh 



14 



1000pF 



A3 




UAF42 



FIGURE 8. PP2 Noninverting Pole-Pair Subcircuit Using External Gain-Set Resistor Re. 



v w o — MA 




NOTE: If R Q = 50W2 when using the PP3 subcircuit, you can 
eliminate the external Q-setting resistor by connecting R 3 as shown 
in Figure 9B. 



FIGURE 9A. PP3 Inverting Pole-Pair Subcircuit. 




FIGURE 9B. Inverting Pole-Pair Subcircuit Using R 3 to Eliminate External Q-Setting Resistor R G . 



165 




O Aux 
Out 



FIGURE 10. PP4 Noninverting Pole-Pair/Zero Subcircuit Using Internal Gain-Set Resistor R 3 . 




FIGURE 1 1. PP5 Noninverting Pole-Pair/Zero Subcircuit Using External Gain-Set Resistor Rg. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



PP6 



V, n O y/W- 



12 



HP Out 



LP Out 



\ 



13 



50k£l 

-vW- 




A, 



r 4 

50kn 



R1 

50k£2 



1000pF 




14 




1000pF 




RZ3 



11 




UAF42 



-O Aux Out 



FIGURE 12. PP6 Inverting Pole-Pair/Zero Subcircuit. 



This subcircuit option requires an external gain-set resistor, 

LP (Real-pole low-pass subcircuit). The basic low-pass 
subcircuit (LP) is shown in Figure 13 A. A single pole is 
formed by R P and C P . A 2 buffers the output to prevent 
loading from subsequent stages. If high input impedance is 
needed, an optional buffer, A b can be added to the input. 

For an LP subcircuit with gain, use the optional circuit 
shown in Figure 13B. 

For an LP subcircuit with inverting gain or attenuation, use 
the optional circuit shown in Figure 13C. 

HP (Real-pole high-pass subcircuit). The basic high-pass 
subcircuit (HP) is shown in Figure 14A. A single pole is 
formed by R P and C P . A 2 buffers the output to prevent 
loading from subsequent stages. If high input impedance is 
needed, an optional buffer, Aj, can be added to the input. 

For an HP subcircuit with gain, use the optional circuit 
shown in Figure 14B. 

For an HP subcircuit with inverting gain or attenuation, use 
the optional circuit shown in Figure 14C. 

IF THE AUXILIARY OP AMP 
IN A UAF42 IS NOT USED 

If the auxiliary op amp in a UAF42 is not used, connect it as 
a grounded unity-gain follower as shown in Figure 15. This 
will keep its inputs and output in the linear region of 
operation to prevent biasing anomalies which may affect the 
other op amps in the UAF42. 



ELIMINATING THE LP SUBCIRCUIT 
IN ODD-ORDER INVERSE CHEBYSHEV 
LOW-PASS FILTERS 

Odd-order Inverse Chebyshev low-pass filters can be simpli- 
fied by eliminating the LP input section and forming the real 
pole in the first pole-pair/zero subcircuit. To form the real 
pole in the pole-pair/zero subcircuit, place a capacitor, C 1( in 
parallel with the summing amplifier feedback resistor, R^. 
The real pole must be at the same frequency as in the LP 
subcircuit. One way to achieve this is to set C] = C P and R^ 
= R P , where C P and R P are the values that were specified for 
the LP section. Then, to keep the summing amplifier gains 
the same, multiply R Z1 and R Z2 by R P /R Z3 . 

Figures 16A and 16B show an example of the modification 
of a 3-pole circuit. It is a 347Hz-cutoff inverse Chebyshev 
low-pass filter. This example is from an application which 
required a low-pass filter with a notch for 400Hz system 
power-supply noise. Setting the cutoff at 347Hz produced 
the 400Hz notch. The standard filter (Figure 16 A) consists 
of two subcircuits, an LP section followed by a PP4 section. 

In the simplified configuration (Figure 16B), the summing 
amplifier feedback resistor, R a is changed from lOkQ to 
130k£2 and paralleled with a 0.01".F capacitor. Notice that 
these are the same values used for R P and C P in the LP 
section of Figure 16 A. To set correct the summing amplifier 
gain, resistors, R Z1 and R Z2 are multiplied by R P /Rz3 ( 1 30kQ/ 
lOkQ). R Z1 and R Z2 must be greater than 2k£i to prevent op 
amp output overloading. If necessary, increase R Z i, R z2 , and 
R^ by decreasing C P . 



167 



LP 




R P 



v 

Optional 
Buffer 




-OV n 



v 

Real Pole 
Section 



, . Real pole f = f^a = 1 /(2n • R P • C P ) [Hz] 
Kl GAIN = 1.0V/V 




Rp 



R 2 



v 

Optional 
Buffer 




v 

Real Pole 
Section 



, b . Real pole f = f^, B = 1/(2rc • R P • C P ) [Hz] 
K "' GAIN = 1 + Rj/R, 




v 

Optional 
Buffer 




v 

Real Pole 
Section 



« Real pole f = f^ B = 1 /(2k • R p • C p ) [Hz] 
1 ' GAIN=-Rp/R, 



FIGURE 13. Low-Pass (LP) Subcircuit: (a) Basic; (b) with 
Noninverting Gain; (c) with Inverting Gain. 



HP 





-ov 



v 

Optional 
Buffer 



v 

Real Pole 
Section 



. . Real pole f = Lmb = 1 'V* ' r p • c p) l Hz l 
W GAIN = 1.0V/V 





v 

Optional 
Buffer 



v 

Real Pole 
Section 



, h . Real pole f = - 1 /(2ic • R P • C P ) [Hz] 
y ' GAIN = 1 + Rj/R, 




HHAAA- 



*2 




Y 

Optional 
Buffer 

, . Real pole f = L ; 
v ' GAIN=-Rj/Rp 



Real Pole 
Section 

.1/(2jr-R P -Cp)[Hz] 



FIGURE 14. High-Pass (HP) Subcircuit: (a) Basic; (b) with 
Noninverting Gain; (c) with Inverting Gain. 




FIGURE 15. Connect Unused Auxiliary Op Amps as 
Grounded-Input Unity-Gain Followers. 



i30kn 

V IN 

c P 4= 

0.01 pF 




549kn- 



13 



1 .37MQ 



50kn 




1 .37M£2 



R,, 50kQ 



C,, 1000pF 



«4 

50kn 




R Z2 , 113WJ 

— MA— i 



14 



C 2 , 1000pF 




5 R Z3 . iokn 



11 




UAF42 



-O Aux Out 



FIGURE 16A. Three-Pole 347Hz Inverse Chebyshev Low-Pass Filter Designed by FilterPro™ Program. 



1.47MO C P ,0.01uF 




O Aux Out 



549kfl 



NOTE: To establish a real pole at the proper frequency and set the proper summing amplifier gain, 
the following changes were made to the pole-pair subcircuit: 

R Z3 changed to R P . 

C P added in parallel with R Z3 . 

R z , and R22 multiplied by Rp/R 23 . 



FIGURE 16B. Simplified Three-Pole 347Hz Inverse Chebyshev Low-Pass Filter (created by moving real pole to feedback of A 4 and eliminating LP input section). 



ON 



Q ENHANCEMENT 

When the f • Q product required for a pole-pair section is 
above =100kHz at frequencies above =3kHz, op amp gain- 
bandwidth limitations can cause Q errors and gain peaking. To 
mitigate this effect, the program automatically compensates 
for the expected error by decreasing the design-Q according to 
a Q-compensation algorithm* u . When this occurs, the value 
under the Q heading on the UAF42 Filter Component Values 
print-out will be marked with an asterisk indicating that it is the 
theoretical Q, not the actual design Q. The actual design Q will 
be shown under an added heading labeled Qcomp- 

USING THE FilterPro™ PROGRAM 

With each data entry, the program automatically calculates 
filter performance. This allows you to use a "what if 
spreadsheet-type design approach. For example; you can 
quickly determine, by trial and error, how many poles are 
needed for a desired roll-off. 

GETTING STARTED 

The first time you use the program, you may want to follow 
these suggested steps. 

Type FILTER42 <ENTER> to start the program. 

Use the arrow keys to move the cursor to the Filter 
Response section. 

1) SELECT FILTER RESPONSE 

Press <ENTER> to toggle through four response choices: 

Low-pass 
High-pass 
Band-pass 
Notch (band-reject) 

When the desired response appears, move the cursor to the 
Filter Type section. 

2) SELECT FILTER TYPE 

Move the cursor to the desired filter type and press 
<ENTER>. The selected filter type is highlighted and marked 
with an asterisk. There are four filter-type choices: 

Butterworth Bessel 
Chebyshev Inverse Chebyshev 

If you choose Chebyshev, you must also enter ripple (i.e. 
pass-band ripple — see Chebyshev filter description). 

If you choose Inverse Chebyshev, you must also enter A MIN 
(i.e. min attenuation or max gain in stop-band — see Inverse 
Chebyshev filter description). 

3) ENTER FILTER ORDER 

Move the cursor to the Filter Order line in the Parameters 
section. Enter filter order n (from 2 to 10). 



(1) L.P. Huelsman and P. E. Allen, Theory and Design of Active 
Filters, p. 241. 



4A) ENTER FILTER FREQUENCY 

Move the cursor to the Filter Frequency line in the Param- 
eters section. 

Low-pass/high-pass filter: enter the f_3 dB or cutoff frequency. 
Band-pass filter: enter the center frequency, fcENTER- 
Band-reject (notch) filter: enter the notch frequency, f notch- 
If your filter is low-pass or high-pass, go to step 5. 

4B) ENTER FILTER BANDWIDTH 

If the filter is a band-pass or band-reject (notch), move the 
cursor to the bandwidth line and enter bandwidth. 

If you press <ENTER> with no entry on the bandwidth line, 
you can enter f L and f H instead of bandwidth. f L and f H are 
the f_ 3dB points with regard to the center frequency for 
Butterworth and Bessel filters. They are the end of the 
ripple-band for Chebyshev types. This method of entry may 
force a change in center frequency or notch frequency. 

5) PRINT-OUT COMPONENT VALUES 

Press function key <F4> to print-out Filter Component 
Values and a Filter Block Diagram. Follow the instructions 
in the filter implementation section of this bulletin to as- 
semble a working filter. 

USING THE PLOT FEATURE 

A Plot feature allows you to view graphical results of filter 
gain and phase vs frequency. This feature is useful for 
comparing filter types. 

To view a plot of the current filter design, press <F2>. 

GRAPHIC DISPLAY COMMANDS 

While viewing the graphic display, several commands can 
be used to compare filter responses: 

<F1> or S — Saves the plot of the current design for future 
recall. 

<F2> or R — Recalls the Saved plot and plots it along with 

the current design. 
<F3> or Z — Plots a Zero dB reference line. 

GRAPHIC DISPLAY CURSOR CONTROL 

While viewing the graphics display you can also use the 
arrow keys to move a cursor and view gain and phase for 
plotted filter responses. 

RESISTOR VALUES 

With each data entry, the program automatically calculates 
resistor values. If external capacitors are needed, the pro- 
gram selects standard capacitor values and calculates exact 
resistor values for the filter you have selected. The 1% 
Resistors option in the Display menu can be used to calcu- 
late the closest standard 1 % resistor values instead of exact 
resistor values. To use this feature, move the cursor to the 
resistors line in the Filter Response section and press 



171 



OP AMP SELECTION GUIDE (In Order of Increasing Slew Rate) 

T A = 25°C, V s - ±15V, specifications typ, unless otherwise noted, min/max specifications are for high-grade model. 





BW 


FPR <" 


SR 


v os 


*OS' u 1 


NOISE 




OP AMP 


typ 


typ 


typ 


max 


max 


at 10kHz 


Cc»< 3 > 


MODEL 


(MHz) 


(kHz) 


(V/us) 


(HV) 


(uV7°C) 


(nV/Vfiz) 


(PF) 


OPA1 77 


0.6 


3 


0.2 


1 


±0.1 


8 


1 


OPA27 


8 


30 


1.9 


25 


±0.6 


2.7 


1 


OPA2107duaM 2 > 


4.5 


280 


18 


500 


±5 


8 


4 


OPA602 W 


6 








±2 


12 


3 


OPA404 quad l 2 > 


6 


500 


35 


1000 


±3 typ 


12 


3 


OPA627 l 2 > 


16 


875 


55 


100 


±0.8 


4.5 


7 


UAF42 aux amp < 2 > 


4 


160 


10 


5000 


±3 typ 


10 


4 



NOTES: (1) FPR is full power response at 20Vp-p as calculated from slew rate. (2) These op amps have FET inputs. (3) Common-mode input capacitance. 



<ENTER>. The program will toggle between exact resis- 
tors and standard 1% resistors. 

CAPACITOR SELECTION 

Even-order filters above 10Hz normally will not require 
external capacitors. Odd order filters require one external 
capacitor to set the real pole in the LP or HP section. 
Capacitor selection is very important for a high-performance 
filter. Capacitor behavior can vary significantly from ideal, 
introducing series resistance and inductance which limit Q. 
Also, nonlinearity of capacitance vs voltage causes distor- 
tion. The lOOOpF capacitors in the UAF42 are high perfor- 
mance types laser trimmed to 0.5%. 

If external capacitors are required, the recommended capaci- 
tor types are: NPO ceramic, silver mica, metallized polycar- 
bonate; and, for temperatures up to 85°C, polypropylene or 
polystyrene. Common ceramic capacitors with high dielec- 
tric constants, such as "high-K" types should be avoided — 
they can cause errors in filter circuits. 

OP AMP SELECTION 

Normally you can use the uncommitted fourth op amp in the 
UAF42 to implement any necessary LP, HP, or gain stages. 
If you must use additional op amps, it is important to choose 
an op amp that can provide the necessary DC precision, 
noise, distortion, and speed. 

OP AMP SLEW RATE 

The slew rate of the op amp must be greater than 
71 * V pp • bandwidth for adequate full-power response. 
For example, operating at 100kHz with 20Vp-p output 
requires an op amp slew rate of at least 6.3V/LIS. Burr-Brown 
offers an excellent selection of op amps which can be used 
for high performance active filter sections. The guide above 
lists some good choices. 

OP AMP BANDWIDTH 

As a rule of thumb, in low-pass and band-pass applications, 
op amp bandwidth should be at least 50 • GAIN • f G , where 



GAIN = noise gain of the op amp configuration and 
f = filter f_ 3dB or f center frequency. 

In high-pass and band-reject (notch) applications, the re- 
quired op amp bandwidth depends on the upper frequency of 
interest. As with most active filters, high-pass filters de- 
signed with the UAF42 turn into band-pass filters with an 
upper roll-off determined by the op amp bandwidth. Error 
due to op amp roll-off can be calculated as follows: 

% = 100 ( 1 - 1 — ) 

\ V (1 + P • (NGAIN)2/(UGBW)2) / 

or 

f = V200-%-V%'UGBW 
NGAIN • (% - 100) 

Where: 

% = Percent gain error f = Frequency of interest (Hz) 

NGAIN = Noise gain of op amp (V/V) 

= GAIN of noninverting configuration 
= 1 + IGALNI of inverting configuration 

UGBW = Unity-gain bandwidth of the op amp (Hz): 



GAIN ACCURACY (%) 


f (NGAIN)/(UGBW) 


-29.29 


1.000 


-10.00 


0.484 


-1.00 


0.142 


-0.10 


0.045 


-0.01 


0.014 



EXAMPLES OF MEASURED 
UAF42 FILTER RESPONSE 

Figures 17 and 18 show actual measured magnitude re- 
sponse plots for 5th-order 5kHz Butterworth, 3dB Cheby shev, 
-60dB Inverse Chebyshev and Bessel low-pass filters de- 
signed with the program and implemented with UAF42s. As 
can be seen, the initial roll-off of the Chebyshev filter is the 
fastest and the roll-off of the Bessel filter is the slowest. 
However, each of the 5th-order all-pole filters ultimately 
rolls off at -N • 20dB/decade, where N is the filter order 
(-100dB/decade for a 5-pole filter). 

The oscilloscope photographs (Figures 19-22) show the step 
response for each filter. As expected, the Chebyshev filter 
has the most ringing, while the Bessel has the least. 



10 


-10 
-20 

a- -so 

C -40 

'co 

O -50 
-60 
-70 
-SO 
-90 









































_ 




















































N ( 






































(( 

A 


























































( 


c) 






i 






































































































(b) 













































50 100 



1k 

Frequency (Hz) 



10k 



50k 



FIGURE 17. Gain vs Frequency for Fifth-Order 5kHz (a) 
Butterworth, (b) 3dB Chebyshev, (c) -60dB 
Inverse Chebyshev, and (d) Bessel Unity- 
Gain Low-Pass Filters, Showing Overall Fil- 
ter Response. 




H Mil 

BH1IIBSS! 




FIGURE 19. Step Response of Fifth-Order 5kHz 
Butterworth Low-Pass Filter. 




FIGURE 20. Step Response of Fifth-Order 5kHz, 3dB 
Ripple Chebyshev Low-Pass Filter. 



3 

-3 
-6 
-9 
-12 
-15 
-18 
-21 
-24 
-27 































(a)- 

41 




























— 


















— \ 










(d) 




















\ 










71- 
\t 




















(b)— 
















































































































(0- 





































100 



1k 

Frequency (Hz) 



10k 



FIGURE 18. Gain vs Frequency for Fifth-Order 5kHz (a) 
Butterworth, (b) 3dB Chebyshev, (c) -60dB 
Inverse Chebyshev, and (d) Bessel Unity- 
Gain Low-Pass Filters, Showing Transition- 
Band Detail. 



ImhI I mhm 



SOduS 



FIGURE 21. Step Response of Fifth-Order 5kHz, 
Inverse Chebyshev Low-Pass Filter. 




FIGURE 22. Step Response of Fifth-Order 5kHz Bessel 
Low-Pass Filter. 



BURR - BROWN 




APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 

INCREASING ADC603 INPUT RANGE 



By Gordon Gleason (602) 746-7494, and R. Mark Stitt 



The ADC603 is a 10MHz, 12-bit analog-to-digital converter 
with a ± 1.25V input range. Many applications call for a 
higher input range such as ±2.5V. A resistor divider can be 
used as an input attenuator to increase the input range. The 
OPA620 can be used to buffer the input attenuator for high- 
source-impedance applications. Suggested component val- 
ues and measured performance results are shown in this 
bulletin. 

Since the ADC603 has a high-impedance input, a simple 
voltage divider as shown in Figure 1 can be used to increase 
its voltage input range. The source impedance of the divider 
as seen by the ADC603 is R, II R 2 (the parallel combination 
of R, and R 2 ). A divider source impedance of 50Q is 
recommended since it has been shown to give consistently 
good results. If a higher divider input impedance is needed 
and adding a buffer is not viable, source impedances up to 
500£2 should give satisfactory results. If hardware gain trim 
is needed, select the next higher 1% resistor value for R, and 
use a 10k£2 multi-turn trim pot in parallel with R, for gain 
trim. 



V,nO 
















R 2 J 

ioon « 








45 / 


ADC603 


~\ 12 Bits 




46 


y out 


R i : 

ioon -= 

















FIGURE 1. ADC603 12-Bit ADC with 2/1 Input Attenuator 
to Provide +2.5V Input Range. 

If an input impedance of 50Q to the circuit is needed as a 
termination, add a third resistor as shown in Figure 2. The 
three-resistor approach improves accuracy by placing the 
majority of the termination power dissipation in the third 
resistor. This minimizes error-producing self heating in the 
precision divider network. Pay attention to the power rating 
for R 3 . For a +10V input, R 3 must be rated 2W. 

If a high input impedance is needed, drive the divider with 
a unity-gain-connected OPA620 buffer amp as shown in 
Figure 3. The OPA620 can be used for inputs as high as 
+3V. 



v, N o « 


















R 2 3 
100Q «= 

100£2 ■> 






66.5£1 - 


-*< 

46 


ADC603 


~\ 12 Bits 

















FIGURE 2. ADC603 12-Bit ADC with Three-Resistor 2/1 
Input Attenuator to Provide ±2.5V Input Range 
and 50i2 Termination Impedance. 



(±2.5V) 




ioon 



R, : 
ioon 



-O +5V 



' 45 ^ ^"aDC603 ^) 1 



12 Bits 
Out 



-O -5.2V 



FIGURE 3. ADC603 12-Bit ADC with 2/1 Input Attenuator 
to Provide High Input Impedance ±2.5V Input 
Range. 

Equations for determining recommended resistor values are: 
R, = 50£2 • N/(N - 1) 
R 2 = (N - 1) • R, 

R 3 = 50Q • (R, + R 2 )/(R, + R 2 - 50Q) 
Where: 

R,, R 2 , R 3 are in £2 
N = input divider ratio 



s 1990 Burr-Brown Corporation 



AB-013 



Printed in U.S.A. July, 1990 



The table below shows recommend resistor values for se- 
lected input ranges. 



INPUT 
RANGE (V) 


DIVIDER 

(1/N) 


R, 

(O) 


(Q) 


R, 

(n) 


±2 


1/1.6 


133 


80.6 


64.9 


±2.5 


1/2 


100 


100 


68.1 


±3 


1/2.4 


86.6 


121 


66.5 


±5 


1/4 


66.5 


200 


61.9 


±10 


1/8 


56.2 


397 


56.2 



TABLE L Resistor Values for Selected Input Attenuators. 



The spectral plots compare a standard ±1 .25V input ADC603 
to a ±2.5V input, OPA620 buffered ADC603 per Figure 3. 
In both cases, the circuit is sampling a 2.5MHz signal at 
10MHz. The results show that the spurious-free dynamic 
range of the boosted circuit is as good as for the standard 
circuit. If anything, the boosted circuit has better perform- 
ance (77dB vs 76dB). The ADC603 seems to perform 
slightly better when driven by the purely resistive 50Q 
divider impedance instead of the complex impedance of the 
cable and signal generator. 



MAGNITUDE SPECTRUM 





-10 
-20 
Ec -30 
£ -40 

2. - 50 
S -60 

1 -70 
S 1 -80 

2 -90 





THD: -73.44dBC 
SNR: 68.07dB 
SINAD: 66.96dB 
SFDR: 75.62dB FSR 
SpurF: 2.66MHz 







1.25 



2.5 

Frequency (MHz) 



3.75 



Plot 1 . Spectral plot of standard ADC603 sampling a ±1 .25V, 
2.5MHz input signal at 10MHz showing 75.6dB SFDR. 



MAGNITUDE SPECTRUM 





-10 
-20 
-30 

^to 

-50 
-60 
-70 
-80 
-90 
-100 
-110 
-120 





THD: -73.49dBC 




SNR: 68.58dB 




SINAD: 67.36dB 




SFDR: 77.14dB FSR 




SpurF: 2.66MHz 







1.25 



3.75 



2.5 

Frequency (MHz) 

Plot 2. Spectral plot of increased input range (per Figure 3) 
ADC603 sampling a ±2.5V, 2.5MHz input signal at 10MHz 
showing 77.1dB SFDR. 



FIGURE 4. Spectral Plots. 



BURR -BROWN® 



I 



1 



APPLICATION BULLETIN 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1 1 1 1 • FAX: (602) 746-7401 



USING THE ADS7800 12 BIT ADC 
WITH UNIPOLAR INPUT SIGNALS 

By R. Mark Stitt and Dave Thomas (602) 746-7445 



The ADS7800 12 bit Sampling analog-to-digital-converter 
is designed to operate with bipolar inputs of +5V or ±10V. 
With the addition of an external amplifier, the ADS7800 can 
be used for 10V or 20V unipolar inputs. Four unipolar input 
options are shown in this Bulletin. 

ADS7800 UNIPOLAR VOLTAGE INPUT RANGES 



INPUT 


SEE FIGURE 


to +10V 


2 


to -10V 


3 


to +20V 


4 


to -20V 


5 



To understand how the circuits work, consider the ADS7800 
input voltage divider network shown in Figure L Since the 
input resistor divider network drives a high impedance at 
V , the transfer function is: 



v =- 



R 3 (R 2 V, + R, V 2 ) 
R, R 2 + R, R, + R 2 R 3 



since R, = R, and R, = 2 R,, 



V o=" 



V, + 2V 2 



Where: 

V, = voltage at pin 1 (V) 
V 2 = voltage at pin 2 (V) 
V Q = voltage into ADC cell (V) 




FIGURE 1. ADS7800 Input- Voltage Scaling Resistor Net- 
work. 

The internal ADC gives a zero to full-scale digital output 
with +2V at V Q (the internal ADC node voltage shown in 
Figure 1). When used in the standard bipolar voltage input 
mode, with V 2 = (i.e. V 2 connected to analog ground), ±10V 
input at pin 1 of the ADS7800 produces ±2V output at V Q . 
Similarly, ±5V input at pin 2 produces ±2V V Q with V, 



grounded. There are four unipolar input range connections 
to the ADS7800 that will produce ±2V V Q when V, or V 2 is 
connected to an appropriate offsetting voltage instead of 
ground. A summary of the four cases is shown in Table I. 



INPUT RANGE 


v, 




v„ 


+5V 


(Ground) 


INPUT 


±2V 


±10V 


INPUT 


(Ground) 


±2V 


to +10V 


-10.000V 


INPUT 


±2V 


to -10V 


+10.000V 


INPUT 


±2V 


to +20V 


INPUT 


-5.000V 


±2V 


to -20V 


INPUT 


+5.000V 


±2V 



TABLE I. ADS7800 Input Ranges (see Figure 1). 

The +2.0V reference output from the ADS7800 can be 
amplified to provide the ±5V or ±10V offsetting voltage 
needed. The circuits in Figures 2 to 5 show how to connect 
inverting or noninverting amplifiers for the various input 
ranges. 

Adjustment of the offsetting voltage is required because the 
absolute accuracy of the 2.0V ADS7800 reference output 
may vary by a few percent. Adjust the lkQ pot for an 
accurate offsetting voltage (e.g. V 2 = 5.000V or V, = 
1 0.000 V). Even though the reference output of the ADS7800 
does not have absolute accuracy, the gain of the ADC is 
scaled to its value. Scaling the internal reference to generate 
the offsetting voltage preserves gain accuracy with tem- 
perature and supply variation so long as the R 4 /R 5 resistor ratio 
tracks with temperature and a low drift op amp, such as the 
OPA177, is used. 

If desired, the ADC zero (negative full-scale) can be adjusted 
by fine trimming the offsetting voltage with the lkQ pot. To 
adjust the ADC zero, apply a 1/2 LSB voltage to the input 
of the ADC and adjust the gain adjust pot so the LSB output, 
pin 17, toggles between 1 and 0. 

The 1/2 LSB zero-adjust voltage can be derived from a 
resistor divider connected to a voltage source (See Applica- 
tion Bulletin AB-003, 004, and 005 for +10V references). 
Remember to consider the input impedance of the ADC 
when using a resistor divider. In the 10V range, the input 
impedance is 2.5kQ + (2.5kQ II 5k£2) = 4.17kQ, in the 20V 
range the input impedance is 5kD + (2.5kQ II 2.5kQ) = 
6.25k£2. Recommended values for a zero-adjust divider are: 



INPUT RANGE 

(V) 


1/2 LSB 
(V) 


v REf 

(V) 


(kfl) 


*m 

(") 


to +10 


0.012 


+10.00 


8.25 


10.0 


0to-10 


-0.012 


-10.00 


8.25 


10.0 


to +20 


0.024 


+10.00 


4.12 


10.0 


to -20 


-O.024 


-10.00 


4.12 


10.0 



®1990 Burr-Brown Corporation 



AB-019A 



Printed in U.S.A. February, 1991 



Oto 10V ( 
In (Vfe) 



-lov.-VW-W-n/W- 1 



R 5 

49.9kQ 



47pF 
'OPA177 




R 4 

9.53k£2 



ft, 
5kO 

2.5kQ 



±2VV 
' to ADC 



R3 
2.5k CI 




Nominal Value of R 5 /R 4 = 50/10. 



FIGURE 2. 1 2-Bit ADC with to 1 0V Unipolar Input Range 
Using the ADC7800. 



Oto -10V 

in(vy 
+iov 




PA177 



47pF 



B, 
5kn 

2.5k£2 



±2VV 
to ADC 



R 5 R4 
39.2kn 9.53kQ 

ikn 



2.5kQ 




Nominal Value of FyR 4 = 40/10. 



FIGURE 3. 1 2-B it ADC with to -1 0V Unipolar Input Range 
Using the ADC7800. 



to 20V 
In (V,) 



-5v — y\v — yyv — vW - 



1k£l 



R 5 
24.3kQ 



47pF 




R4 
9.53k£l 



ADS7800 



ft, 
5kfl 

R 2 
2.5kfl 



±2VV 
to ADC 



R3 
2.5kn 




Nominal Value of R/R, = 25/10. 



FIGURE 4. 1 2-Bit ADC with to 20V Unipolar Input Range 
Using the ADC7800. 



Oto -20V, 
In M) 



+5V 




PA177 



47pF 



r ADS7800 



2.5kR 



14.7kn i 9.53k£l 

i — AY — vVV — 



1k£l 



Ra 
2.5kf2 




Nominal Value of R s /R, = 15/10. 



FIGURE 5. 1 2-Bit ADC with to -20V Unipolar Input Range 
Using the ADC7800. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR -BROWN® 



APPLICATION BULLETIN 

I Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 

FREQUENCY-TO-VOLTAGE CONVERSION 

By R. Mark Stitt and Rod Burt (602) 746-7445 



Precision frequency-to- voltage converters (FVC)s can be 
made using voltage-to-frequency converters (VFCs). 
Burr-Brown offers a complete line of precision free- 
running VFCs. 

VFC110 High frequency, low jitter VFC 

4MHz max full-scale, +0.02% typ linearity at 
2MHz 

VFC121 Precision single-supply VFC (+4.5V to +36V) 
1.5MHz max full-scale, 0.03% max 
nonlinearity at 100kHz 

VFC320 Precision VFC 

1MHz max full-scale, 0.005% max 
nonlinearity at 10kHz 

This bulletin describes three techniques for making a 
precision FVC using a VFC. The standard technique has 
high precision, but high ripple or slow settling. Adding an 
output filter can improve the settling-time, ripple trade- 
off, but adds error. A third new technique can eliminate 
ripple from the FVC output and improve settling time by 
more than 1000/1 as compared to the conventional FVC. 
Moreover, the DC precision is unaffected. 



FVC APPLICATIONS 

A rapidly-growing application for frequency-to-voltage 
converters is high-voltage analog signal isolation. High- 
voltage analog isolation amplifiers (ISO Amps), such as 
the Burr-Brown IS0121, are available for isolating signals 
up to 8000V. Higher voltage isolation of tens-of-thou- 
sands or even millions of volts as in utility-power-trans- 
mission line monitoring, nuclear event monitoring, and 
protection from lightning strikes calls for other tech- 
niques. You can get virtually unlimited isolation by using 
a voltage-to-frequency converter (VFC) to digitize an 
analog signal and transmit it over a fiber-optic data link to 
a FVC where the signal is reconstructed. 

Many times VFCs are favored for analog-to-digital con- 
version because of their integrating input characteristic 
and high resolution (modern Sigma-delta analog-to-digi- 
tal converters are really a variation of a VFC with digital 
filtering and encoding). An analog signal digitized by a 
VFC can be transmitted to a remote receiver serially over 
a single twisted pair wire cable or isolated with a single 
optical isolator. At the other end, the digital signal can be 



+5V 

p 



14 



(TTL) 



inO 1 



11 



C, - 
1000pF 



10 



14 



9 



B V s R, NT 
Q 



SN74121 
One Shot 



R/C E> 




Q 6, 



'"'EXT 

Gnd A. A, 



:ikn 



10 



;R 2 

• 7.5kTi 



R 6 
40kfl 



VFC320 




:> 


One 




Shot 









13 



"o 
-O 



12 

-p 3300pF 

_ NPO 

— 



-15V +15V 



FIGURE 1 . A Conventional Frequency-to- Voltage Converter. This FVC can be made by connecting a Burr-Brown VFC320 
voltage-to-frequency converter in the FVC Mode. Select C 3 for ripple/settling-time trade off. 



®1992 Burr-Brown Corporation 



AB-040 



Primed in U.S.A. April, 1992 



both digitally processed and reconstructed to analog. An 
analog signal is often required, as in medical applications, 
for bedside monitoring on a CRT or LCD display. The 
fast-settling, ripple-free characteristics of the FVC de- 
scribed here makes it ideal for this application too. 

THE CONVENTIONAL FVC 

In an conventional FVC, a one-shot-controlled current 
reference is averaged. A serious problem with the conven- 
tional FVC results from a trade-off between ripple and 
settling time. Improved resolution from the FVC demands 
low ripple, but decreasing the ripple increases settling 
time. 

An example of a conventional FVC circuit is shown in 
Figure 1. It uses a Burr-Brown VFC320 voltage to fre- 
quency converter connected in the FVC mode. The 
SN74121 one shot along with input resistors, R,, R 2 , and 
pull-up resistor Rg convert a TTL-logic-level input into a 
1 |0.s negative-going pulse to trip the ground-referenced 
comparator in the VFC320. When tripped, the comparator 
triggers a precision one shot in the VFC320. When trig- 
gered, a 1mA current reference in the VFC320 is switched 
to the input of an averaging transimpedance amplifier for 
the period of the one shot. 

The transimpedance amplifier can be thought of as an 
integrator consisting of an op amp in the VFC320 with an 
external integrating capacitor, C 3 . A current proportional 
to the integrator output voltage is summed in through 



feedback resistor, R 6 . Both the periodic 1mA current pulse 
and the current through R 6 are integrated in C 3 . The 
average voltage at the output of the integrator is propor- 
tional to the input frequency, the precision one-shot pe- 
riod, the current reference, and the external feedback 
resistor, R 6 . 

The duration of the one-shot period is determined by the 
external one-shot capacitor, C 2 . In this example, the one- 
shot pulse-width is set at 25|is for a full-scale FVC input 
range of 10kHz. It has been empirically determined that 
best VFC or FVC linearity is obtained when the one shot 
pulse width is approximately 25% of the full-scale input 
period. 

The integrator output ramps up during the one-shot pe- 
riod, integrating the sum of the 1mA current source and 
the current through the feedback resistor. Then, the one- 
shot output ramps down during the balance of the input 
frequency period, integrating only the current through the 
feedback resistor. The peak-to-peak value of this ramp 
appears at the FVC output as ripple. 

The value of the integrator capacitor affects the FVC 
output ripple, but does not affect the average DC output 
voltage. Increasing the value of the integrator capacitor 
decreases the voltage ripple, and increases the time for the 
integrator output to settle for a change in input frequency. 
Settling time follows a single pole response. The follow- 
ing relationships apply for the conventional FVC: 



FinO 1 



+5V 

O 



C, - 
1nF" 



10 



14 



INT 

Q 



SN74121 
One Shot 



Ryc^ 

Cext 
Gnd 



i M 



14 



10 



;R 2 

■ 7.5kn 



11 



R 6 

40k£i 

Hr— 

0.04pF 
VFC320 




12 



13 



100Hz 3-Pole 



-12.1k£2 



-II— 

220nF 












19.1W2 




OPA602^> _< 






+ 



4.22kQ 



: 100nF 



=^68nF 



6 ■=" 
-15V +15V 



C 2 
: 3300pF 
NPO 



FIGURE 2. A Conventional Frequency-to- Voltage Converter. This converter with a 3-pole low-pass Bessel filter added to 
the output has less than lmV ripple at 1.2kHz and can settle to 0.01% in 18ms. 



179 



V 0= F IN* T OS* I R* R 6 

(same for conventional and fast-settling FVC) 
RIPPLE m T os • I R /C 3 

/ 100% \ 

Where: N ' 

V = Average output voltage [V] 

F^ = Input frequency [Hz] 

(10kHz full-scale in this example) 

I R = Current reference [A] 
(1mA for the VFC320) 

T os = One-shot period [s] 
(25us in this example) 

t s = time for the output to settle to desired tolerance [s] 

R 6 = Integrator feedback resistor 

(40k£2 for 10V full scale output with 10kHz 
input) 

RIPPLE = Variation in V [Vp-p] 

C 3 = Value of integrator capacitor [F] 

P = Desired precision of the output signal 
[% of full-scale] 

CONVENTIONAL FVC PERFORMANCE 

The conventional FVC has excellent DC performance, but 
poor dynamic performance. For example, consider an 
FVC with 10V full-scale output for 10kHz input. Using 
the VFC320 voltage-to-frequency converter with I R = 1mA 
and T os = 25|is, R 6 must be 40k£2. In the conventional 
FVC, for 0.01% resolution (lmV ripple), C 3 must be set to 
25|iF and settling time is an astoundingly long 9.2s. 

FILTERING THE CONVENTIONAL FVC 

In practice, the settling-time/ripple trade-off of the con- 
ventional FVC can be improved substantially by filtering 
the FVC output with a higher-order low-pass filter as 
shown in Figure 2. In this approach, a conventional FVC 
is designed with relatively high output ripple to give fast 
settling time. Then a high-order low-pass filter is added in 
series with the FVC output to reduce the ripple. 

In the Figure 2 example, a value of 40kQ was used for R 6 
to set a 10V full-scale output for a 10kHz input. A value 
of 0.04(iF is used for C 3 giving approximately 625mV 
max ripple. This is an arbitrary but adequate value to give 
excellent linearity and a 10V full-scale output. Higher 
ripple would reduce the linear output range of the FVC 
because, at full-scale output, the FVC must swing 10V 
plus approximately one half the ripple voltage. 

There are many output filter possibilities for a filtered 
FVC. Because of its excellent pulse response a Bessel 
filter gives the fastest settling of any standard filter type. 
The tables below show examples of FVC performance for 
Bessel filters of order 2 through 5. The 3-pole Bessel filter 
gives a good settling-time complexity trade-off. Figure 2 
shows the conventional FVC with a 3-pole Sallen-Key 



Bessel filter. With the filter f_ MB frequency set to 100Hz, 
ripple at 1.2kHz is below lmV and settling time to 0.01% 
is 18ms. Notice that ripple increases dramatically below 
1.2kHz when higher-order filters are used. 



FILTERED FVC PERFORMANCE WITH BESSEL FILTER 









SETTLING 


RIPPLE 


RIPPLE 


FILTER 


f-3dB 




(0.01%) 


(at 1.2kHz) 


(at 400Hz) 


ORDER 


(Hz) 




(ms) 


(mV) 


(mV) 


2 


35 




38 


1 


8 


3 


100 




18 


1 


25 


4 


155 




17 


1 


59 


5 


205 




17 


1 


134 



The Sallen-Key filter architecture, used for the low-pass 
filter, was selected for low gain error. You can't include 
the filter in the feedback loop because the excessive 
phase-shift would cause instability. Since the filter must 
be added outside the integrator feedback loop, DC errors 
such as gain offset and offset drift add to the transfer 
function of the FVC. In the unity-gain Sallen-Key archi- 
tecture, the op amps are connected as voltage-followers so 
gain error is negligible. You still must use low-drift 
precision op amps to reduce offset and offset drift errors. 
Other active filters can be designed with easy-to-use 
DOS-compatible programs available free of charge from 
Burr-Brown— request the FilterPro™ filter design soft- 
ware. These programs make it easy to design a wide 
variety of practical Sallen-Key, Multiple Feedback (MFB), 
and State- Variable active filters up to tenth order. State- 
Variable active filters use the UAF42 monolithic Univer- 
sal Active Filter which contains on-chip precision capaci- 
tors so that external capacitors are not required. 

The filtered FVC gives a good improvement in settling 
time. However, even with the complexity of a 3-pole 
filter, its performance pales in comparison to the fast- 
settling FVC. Filtering, with a 3-pole filter, can give 18ms 
settling to 0.01% with less than lmV ripple at 1.2kHz, but 
ripple increases at lower frequencies. For comparison, the 
new fast-settling FVC, using the same P^, C 3 values, 
settles to 0.01% in 7.4ms with less than lmV ripple at any 
frequency. 

THE NEW FAST-SETTLING FVC 

Instead of using a filter in series with the output, the fast- 
settling FVC uses a sample/hold amplifier inside the 
integrator feedback loop of the conventional FVC. One 
way to think of the fast-settling FVC is as a conventional 
FVC with an adaptive N-pole filter in its feedback. The 
order, N, of the adaptive filter approaches a very high 
value so that all integrator output ripple is removed 
regardless of input frequency. By comparison, the output 
ripple of the filtered FVC increases with decreasing fre- 
quency. Also, delay of the adaptive filter is low so that it 
can be included in the feedback loop to the integrator 
without adversely affecting stability. This is not possible 
with a conventional filter. With the filter included in the 
feedback loop, DC filter errors (sample/hold errors) such 
as gain, offset, and offset drift are divided-down by the 
loop gain of the integrator amplifier to negligible levels. 



and C 3 . In theory, a smaller value could be used for C 3 in 
the fast-settling FVC for better settling time. Ripple at the 
output is eliminated by using a sample/hold to sample the 
VFC320 integrator output. The only constraint on ripple 
voltage is that it must be within the linear output-swing 
range of integrator amplifier. Gain can be added in the 
sample/hold circuit to reduce the peak amplitude needed 
from the integrator output. In the filtered approach, added 
gain would also gain-up the ripple. 

In the fast-settling FVC, the sample/hold acquires a feed- 
back signal from the integrator output ramp in approxi- 
mately lus so that the ripple of the ramp is translated to 
a higher frequency and substantially eliminated by a 
simple single-pole high-frequency filter, R 5 , C 5 . The delay 
through the high-frequency filter is low enough so that it 
can also be included in the feedback loop. 

Since the sample/hold is in the feedback loop of the 
integrator, trigger timing is unimportant. The feedback 
loop automatically adjusts the relative level of the integra- 
tor output signal for proper alignment with the trigger 
pulse. 



verier connected as a level shifter. Pull-down resistor Rg is 
added at the output of the integrator amplifier to boost 
output drive to the sample/hold capacitor, C 4 . 

Design of the sample/hold is greatly simplified because 
DC accuracy is unimportant. The complete sample/hold 
circuit consists of a common DMOS FET, Q,, hold ca- 
pacitor, C 4 , and FET-input op amp, A,. High frequency 
sampling glitches are also filtered out by the R 5 , C 5 output 
filter. Since the glitch filter is also in the integrator 
feedback loop, associated DC errors are eliminated, and 
low DC output impedance is maintained. 

Sample/hold gain is set to 2.0V/V by R 3 and R 4 . The 
sample/hold gain attenuates (by two) the maximum output 
excursion necessary from the VFC320 integrator output, 
allowing both a comfortable +10V full-scale output from 
the FVC and a large ripple signal at the integrator output. 

Gain in the feedback loop of the integrator also increases 
slew rate and bandwidth. With a high slew-rate op amp 
used for A,, FVC slew rate is limited by the integrator op 
amp. Adding a gain of two in the feedback loop doubles 



+15V 



+5V 

(TTL. 10kHz FS) 




SN7406 



.10kfl 



14 



10 



• 7.5ki2 



1 1 0.04pF 
Polystyrene 



VFC320 




12 



13 



R 8 

40kn 

-vW- 




Q, (1 > 



R 3 > 

^okn^. I c 4 

"0.01(JF 




-15V 



NOTE: (1) Siloconix Type SD214DE DMOS FET. 



: 3300pF 
NPO 



— 
15V +15V 



FIGURE 3. Fast-Settling Frequency-to- Voltage Converter. This converter is formed by adding a sample/hold in the feedback 
loop of the conventional FVC. It can settle to 0.01% in 7.4u.s without ripple. Because the sample/hold is in the 
feedback loop, FVC precision is unaffected. 




1mAT VF C320 
Fragment 



Linear 




Gain 


Delay 




Block 
G = 2 



Low-pass Sample/Hold 
Number 1 



Low-pass 
Number 2 

R5.C5 



FIGURE 6. This Integrator Feedback-Loop Block Diagram can be Used for Stability Analysis of the Fast-Settling FVC. 




FIGURE 7. Dual-Trace Scope Photo Showing Frequency- 
to- Voltage Converter IV to 9 V Output for a 
1kHz to 9kHz TTL-Level Frequency Input. 



The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility lor inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



1.2kHz to 10kHz 
frequency 



1.2V to 10V 
square-wave 
input c 



Voltage 


Output Input 


Frequency 


-to- 




-to- 


Frequency 




Voltage 


Converter 




Converter 


(VFC) 




(FVC) 



Precision 
Difference Amplifier 




FVC Settling-Time Test Circuit 



1.2V to 10V 
square-wave 
output 



Error signal 
see Note 1 . 



1 



NOTE: (1) Settling-time error signal (FVC Input) — (VFC Output) 
see scope photo Figure 5. 



FIGURE 5A. FVC Settling-Time Measurement Circuit 
Used for Figure 5. 

DISCUSSING STABILITY 

OF THE FAST-SETTLING FVC 

Stability in sampled systems depends on sampling fre- 
quency. Since the sample/hold in the feedback loop of the 
fast-settling FVC is controlled by the input frequency, 
there is a minimum input frequency required to assure 
loop stability. As input frequency decreases, delay through 
the sample/hold increases thereby decreasing phase mar- 
gin of the integrator loop. The feedback loop block dia- 
gram shown in Figure 6 gives a fairly accurate stability- 
criteria analysis. Phase margin of the loop is as follows: 

MARGIN = 180° - 90° - delay, - delay 2 - delay. 



Where: 

MARGIN = phase margin of the loop 

90° = phase delay of the R 6 , C 3 dominant pole 

delay, = delay of sample-hold switch, Q,, and hold 
capacitor, C 4 

delay, = Tan '(f UG • 2 • ji • Rq, • Q 

delay 2 = delay due to R 5 , C 5 output filter 

delay 2 = Tan-'ffuo • 2 • n • R 5 • C 5 ) 

delay 3 = delay due to sample period 

360 • f UG 
delay, = — — - — 

f uo = unity-gain frequency of the overall integrator 
loop 

f UG = GAIN/(2.7t.R 6 .C3) 

GAIN = gain of the sample/hold circuit in the feedback 
loop 

Solving for f m , 

(See Equation Below) 

Where, in addition to previous definitions: 
R Q , = On-resistance of sample/hold switch-transistor, 
Q, [Q] 

Substituting the values from Figure 3, and using 25Q for 
R Q „ gives the following results: 



MARGIN 




o 


(Hz) 


60 


1200 


45 


780 


30 


600 





400 



For best pulse response and settling time the minimum 
input frequency should be 1.2kHz for the Figure 3 circuit 
example. At input frequencies below 400Hz, the loop will 
be unstable and the output will oscillate or lock-up. 



t -90° «Gain 


IN 


r 

Margin -90°+ tan" 1 


( Gain-R s » 


+ tan 1 


''Gain »R„ »CA 

Ql 4 


\ 
I 


K 6 3 J 


V, 6 3 ) 



183 



the FVC slew rate. The actual sample/hold gain is not 
critical. Because it is in the feedback loop, gain errors in 
the sample/hold circuit do not affect the gain of the FVC 
or degrade its accuracy. 

FAST-SETTLING FVC PERFORMANCE 

The fast-settling FVC has the same DC transfer function 
as the simple FVC, but with neglegable ripple at the 
output. Measured DC performance of the Figure 3 FVC 
circuit gave nonlinearity better than lOppm (better than 16 
bits). 

The scope photo in Figure 4 shows the excellent small 
signal ±1 V (actually +6V to +8V) output step response for 
the FVC with a 6kHz to 8kHz input frequency change. If 
phase margin were low, this signal would exhibit over- 
shoot and ringing. 

Settling time of the fast-settling time FVC approximates 
that predicted by a single-pole system boosted by the gain 
in the feedback loop: 

100% . 

R 6 • Cj/GAIN 



-In (™*\ 



Where: 

GAIN = Gain of sample/hold circuit in feedback loop 
of integrator [V/V] 

With R 6 = 40kQ, C 3 = 0.04u.F, and GAIN = 2.0V/V as 
shown in Figure 3, 7.4ms settling to 0.01% is predicted. 
The scope photo in Figure 5 shows good agreement 
between theoretical and measured settling time for a large 
signal +1.2V to +10V output step due to a 1.2kHz to 



10kHz input frequency change. The scope photo shows 
the residual error signal superimposed on the theoretical 
output signal. Each graticule division is approximately 
0.01%. 

The circuit used to measure settling time is shown in 
Figure 5 A. A +1.2V to +10V square wave is applied to the 
input of both a VFC and to a precision difference ampli- 
fier. This square-wave input is the theoretical output 
signal — shown as one of the two traces on the scope photo 
Figure 5. The VFC converts the input voltage square wave 
into a modulated TTL-level 1.2kHz to 10kHz frequency 
signal. The frequency signal feeds directly into the FVC 
under test. The output of the FVC, ideally a delayed 
reproduction of the input square wave, feeds into the 
inverting input of the difference amplifier. The difference 
amplifier subtracts the FVC output from the VFC input. 
The output of the difference amplifier, (FVC output)- 
(VFC input) is the residual error signal — shown as the 
second trace on scope photo Figure 5. For this method to 
work, the VFC must have small dynamic error compared 
to the FVC. The VFC used in these measurements was the 
Burr-Brown VFC320. 

Scope photo Figure 7 is a picture of a sine-wave modu- 
lated 1kHz to 9kHz TTL-level (0V to 5V) FVC input 
signal superimposed on the IV to 9 V FVC output. This 
photo was taken by driving a IV to 9V sine- wave signal 
into the Figure 5A test circuit and looking at the FVC 
input and output. At the lower 1kHz frequency input, the 
steps between frequency input pulses can be seen on the 
sine-wave output showing excellent settling between pulses. 




FIGURE 4. Small-Signal Step Response of the Fast- 
Settling FVC Shows Excellent Stability. 



FIGURE 5. Settling Residue of the Fast-Settling FVC 
Confirms 0.01% Settling is Approximately 
7.4ms. 



HIGH SPEED DATA CONVERSION 

By Mike Koen (602) 746-7337 



IOC 



INTRODUCTION 

The design considerations for high-speed data conversion 
are, in many ways, similar to those for data conversion in 
general. High speed circuits may sometimes seem different 
because device types can be limited and only certain design 
techniques and architectures can be used with success. But 
the basics are the same. High speed circuits or systems are 
really those that tend to press the limits of state-of-the-art 
dynamic performance. 

This bulletin focuses on the more fundamental building 
blocks such as op amps, sample/holds, digital to analog and 
analog to digital converters (DACs and ADCs). It concludes 
with test techniques. Op amps, which tend to be the basic 
building blocks of systems, are be considered first. Sample/ 
holds which play an important role in data conversion are 
considered next followed by DACs and finally ADCs. ADCs 
are really a combination of the other three circuits. Emphasis 
is given to hybrid and monolithic design techniques since, in 
practice, the highest levels of performance are achieved 
using these processes. The material is presented from a 
design perspective. Theory and practical examples are of- 
fered so both the data conversion component designer and 
user will find the material useful. The concepts presented do 
not require extensive experience with data conversion. Fun- 
damental concepts are discussed allowing the subject to be 
understood easily. The material emphasizes high speed cir- 
cuit considerations — circuit theory is not treated in depth. 

Topics Covered in this Bulletin 

A. Amplifier Architectures 

1. Buffer 

2. Operational 

3. Open Loop 

4. Comparator 

B. Amplifier Applications 

1. Sample/Hold 

2. Peak Detector 

C. Digital to Analog Converters 

1. Bipolar 

2. Deglitched DAC 

D. Analog to Digital Converters 

1. Successive Approximation 

2. Flash 

3. Sub-ranging 

E. Test Techniques 

1. Settling Time 

2. Aperture Jitter 

3. Beat Frequency Testing 

4. Servo Loop Test 




FIGURE 1. High Speed Bipolar Buffer. 
AMPLIFIER ARCHITECTURES 

Amplifiers of all types play an important role in data 
conversion systems. Since high speed amplifiers are both 
useful and difficult to design, an understanding of their 
operation is important. Four different types of amplifier 
architectures will be discussed. Buffers, op amps, open loop 
amplifiers, and comparators can be found in just about any 
signal processing application. 

THE BUFFER 

The open loop buffer is the ubiquitous modem form of the 
emitter follower. This circuit is popular because it is simple, 
low cost, wide band, and easy to apply. The open loop buffer 
is important in high speed systems. It serves the same 
purpose as the voltage follower in lower speed systems. It is 
often used as the output stage of wideband op amps and 
other types of broadband amplifiers. Consider the two buffer 
circuit diagrams, Figures 1 and 2. The output impedance of 
each buffer is about 5£2 and bandwidths of several hundred 
megahertz can be achieved. The FET buffer is usually 
implemented in hybrid form as very wideband FETs and 
transistors are usually not available on the same monolithic 
process. The all-bipolar form of the buffer is capable of 



r- 

CM 

i~ 

0) 

.o 
E 

3 

z 

C 
♦3 
0) 

3 
CD 

c 
o 

CO 

o 

Q. 
Q. 
< 



®I991 BurT-Brown Corporation 



AB-027A 



Printed in U.S.A. June, 1991 







v+ 




OUT 



V- 



FIGURE 2. High Speed FET Buffer. 

being produced on a complementary monolithic process 
where both the NPN and PNP transistors are high perfor- 
mance vertical structures. Figure 1 shows the buffer in its 
most basic form. The input to the buffer is connected to a 
pair of complementary transistors. Each transistor is biased 
by a separate current source. The input transistors Qj and Q 2 
through resistors R { and R 2 are connected to the bases of 
output transistors Q 3 and Q 4 so that offset will be zero if the 
base to emitter voltage of the NPN and PNP are equal. Zero 
offset requires that transistor geometries are designed for 
equal V BE s at the same bias current — achievable in a 
complementary process. This circuit is very useful as it has 
a moderately high input impedance and the ability to supply 
high current outputs. One important use of this buffer circuit 
is to amplify the output current of a monolithic op amp. 
Monolithic op amps usually do not have output currents that 
exceed 10mA to 50mA, while the buffer shown in Figure 1 
is capable of putting out more than 100mA. Typically this 
type of a buffer has a bandwidth of 250MHz, allowing it to 
be used in the feedback loop of most monolithic op amps 
with minimal effect on stability. Figure 3 shows how the 
loop is closed around the buffer so that the DC performance 
of the amplifier is determined by the unbuffered amplifier 
and not the output buffer. An advantage of the connection 
shown in Figure 3 is that load-driving heat dissipating is in 
the buffer so that thermally induced distortion and offset 
drift is removed from the sensitive input op amp. 

Figure 2 shows the FET version of the previously mentioned 
circuit. The FET buffer achieves zero offset by the mirror 
action of the NPN transistor Q 5 that is reflected as the gate 



R, R 2 




FIGURE 3. High Current Op Amp. 

to source voltage of the input FET Qj. The V BE of Q5 
determines the gate to source voltage of the FET current 
source Q 4 . Since the identical current flows in Q 4 and Qi the 
gate to source voltage of Qj will also be equal to V BE . Since 
Q 5 and Q 6 are identical transistors the offset of the FET 
buffer circuit will be nominally zero. The circuit shown in 
Figure 2 is usually constructed in hybrid form so that it is 
usually necessary to adjust resistors R] and R 2 to set the offset 
of this circuit to zero. Setting the offset to zero is accom- 
plished by laser-trimming resistors R! and R 2 with the buffer 
under power. (This is known as active trimming.) A com- 
mon application of this circuit is to buffer the hold capacitor 
in a sample/hold. (See the section on sample/holds.) The 
high impedance of the FET buffer allows the capacitor to 
retain the sample voltage for a comparatively long time as 
the room temperature input current of a typical FET is in the 
vicinity of 50pA. 

Another common application of either type of buffer circuit 
is to drive high capacitive loads without reducing the overall 
system bandwidth. Op amps, even though they have closed 
loop output impedances that are very low, can become 
unstable in the presence of high capacitive loads. The open 
loop buffer is usually more stable when driving capacitive 
loads, but this circuit will also develop a tendency to ring if 
the capacitive load becomes excessive. Figure 4 shows how 
the emitter follower can oscillate due to reactive output 
impedance. Figures 5 through 7 show calculated results for 
different conditions when a simple emitter follower is driv- 
ing a capacitive load which illustrates this oscillatory ten- 
dency. 

One very important application of the open loop buffer is to 
drive a "back matched" transmission cable. Back matching 
a cable is just as effective in preventing reflections as the 
more conventional method of terminating the cable at the 
receiving end. The advantage of the back matched cable is 
that the generating circuit does not have to supply steady- 
state current and there is no loss of accuracy due to the 
temperature dependent copper loss of the cable. Figure 8 
shows circuit diagrams and explanations that describe the 
operation of the open loop buffer driving a "back matched" 
cable. 



187 



THE OPERATIONAL AMPLIFIER 

Several examples will be shown that depict the architecture 
of wideband op amps. These amplifiers have settling times 
to ±0.01% in under 100ns and closed loop bandwidths in 
excess of 100MHz. The question is often asked, "How much 
loop gain is enough?" Wideband amplifiers generally do not 
achieve as much open loop gain as lower frequency ampli- 
fiers. This is the result of optimization of bandwidth and 




v+ 

J 

Q, 



-ov n 



Z 0UT = re + - 



R G + rb 
P(o>) 



PM- 



P(o) 



o)p= 

P(o) 
Zqut - re + 



1+ <-^p 



R G + rb j o> (R G + rb) 



m 

Z OUT = R EO + j(oL EQ 



FIGURE 4. Output Impedance of Emitter Follower. 



A t 



where: T = 2ji (L EQ • C L ) 2 

"eq + 1 1 T 

R Q + rb 

: re + — 

P(o) 

R G + rb 



Lec- 



tor 



FIGURE 5. Time Response. 



f T = 1GHz 


f T = 5GHz 


f T = 5GHz 


R G = 50Q 


R G = 50Q 


r g = soa 


rb-50 


rb = 50 


rb = 50 


re = 5 


re = 5 


re = 5 


C L = 50pF 


C L = 50pF 


C L = 50pF 


p(o) = 100 


P(o)- 100 


P(o) = 100 


k = 0.35 


k = 0.44 


k = 0.51 


T = 5.6ns 


T = 4.7ns 


T = 1.9ns 



phase margin. If open loop gain is stable over temperature 
and linearity with signal adequate, the requirement for high 
open loop gain is reduced. This is important since it is 
difficult to achieve high open loop gain for wideband ampli- 
fiers. 

There are several ways to shape the open-loop-gain/phase 
characteristics, or Bode Plot, of an amplifier. The method 
chosen depends on whether high slew rate or fast settling is 
to be emphasized. The methods of stabilizing the closed- 
loop gain of these amplifiers will also result in different 
settling time characteristics. The benefits of each of these 
methods will be explained. The first amplifier has a FET 
input and the other has a bipolar input. High speed amplifi- 
ers should be designed to drive 50Q loads to be most useful. 
50£2 cable is commonly used in high speed systems to 
interconnect signals. 





1.4 




1.2 


CD 
TD 


1.0 






mpli 


0.8 


< 








■ 


0.6 






o> 




C 


0.4 




0.2 
















— k 


= 0.35, 


T = 5. 


Bns 






























I.44, T 


= 4.7n 














-k = ( 


s 








k 


= 0.51, 


T= 1. 


3ns 















































4 5 
Time (ns) 



FIGURE 7. Results. 




ov 



1 



t 



Cable 
Input 



± 



V 



Received 



V/2 



♦ 



,_L_ 

J V/2 



V/2 



Reflected 



V/2 



V 



FIGURE 6. Different Conditions. 



FIGURE 8. Back Matched Cable. 













1 — 1 




Q 5 i— 


Q8 







R 9 C, 

■VW — |(- 



+ln O- 



R 2 



Pole-Zero 
Comp 



C 2 ^ 



To V-l 



-In O- 




R 3 



Integrator 
Compensation 





ToV- 



X 



-ov+ 



a«T]— * ^ £a 





-ov n 



-ov- 



FIGURE 9. FET Operational Amplifier. 



Consider a classic two stage hybrid amplifier as shown in 
Figure 9. It can be compensated either with integrator 
feedback or with pole-zero compensation. Hybrid amplifiers 
can achieve the highest possible dynamic performance be- 
cause optimum input and output devices that can be used 
from widely differing technologies. Very often it is possible 
to achieve the combination of bandwidth, breakdown volt- 
age, and current levels needed only with hybrid techniques. 
It is instructive to analyze the performance of this amplifier 
in detail as a way of demonstrating many pertinent consid- 
erations for a high speed amplifier. High speed amplifiers 
may be configured in other ways but the major design 
considerations are the same. FET input amplifiers are very 
useful as their high input impedance serves to buffer the hold 
capacitor in sample and hold circuits. Additionally, a FET 
can tolerate much larger differential input voltages during 
overload conditions than bipolar input stages and there is no 
error due to input current. 

The input stage of the amplifier shown in Figure 9, draws 
5mA per side and at 25°C the input current is typically 
25pA. A bipolar input stage being operated at the same 
current would have an input current of approximately 50uA, 
which when transformed by the feedback resistor, would be 
an additional source of offset error and noise. To compen- 
sate for the low gain of the input stage (G = 25) it is desirable 



to maintain a differential connection between the first and 
second stages. When a connection of this type is made it is 
necessary to establish the operating point of the input stage 
using "common mode" feedback. Assuming that FET pair 
Q 2 and Q 3 are well-matched, the current is split evenly and 
emerges as equal collector current for transistors Q 4 and Q5. 
The bases of Q 4 and Q5 are connected together and applied 
to the common connection of the emitters of PNP transistors 
Q 8 and Q 9 . Therefore, in order to establish balance in the 
loop, a voltage is created across R 7 of such a magnitude to 
allow the current in transistors and Q 4 to be a value that will 
exactly balance the current needed by FETs Q 2 and Q3. 
Transistors Q 8 and Q9 a driven from a pair of emitter fol- 
lowers to increase the overall loop gain. Emitter follower 
transistors Q 6 and Q 7 increase the gain of the first stage by 
preventing transistors Q 8 and Q 9 from loading the drains of 
the input FET pair. The differential output of transistors Q g 
and Q 9 are then connected to the output emitter followers 
directly and through the mirroring action of transistors Q 12 
and Q 13 . The overall DC gain of this amplifier is 94dB. The 
current through the output emitter follower is established by 
the biasing action of the diode connected transistors Q 10 and 
Qi i- The offset voltage of this amplifier is trimmed to under 
lmV and the amplifier has a voltage offset drift coefficient 
of less than 10uV/°C. 



189 



'00 



it- 




-OV+ 




-ov- 



G = 



1 AP 



P 1+AP 



A(co) = 



A(o) 



Pole Second 
Due to Pole 
Integrator 



FIGURE 10. Integrator Compensation. 

As previously mentioned, there are two methods for com- 
pensating the open loop frequency response of this ampli- 
fier. The first method to be discussed is called integrator 
feedback as a capacitor is connected from the output stage to 
the drain of the input stage. Figure 10 shows a block diagram 
of this connection which more clearly demonstrates why it 
is called integrator compensation as an integrator is formed 
around the output gain stage of the amplifier. The advantage 
of integrator feedback is that the closed loop frequency 
response has all the poles in the denominator which means 
that the transient response is tolerant to parameter variation. 
As will be shown, another type of frequency compensation 
is called "doublet" or "pole-zero cancellation" which can 
have poor transient response due to small parameter varia- 
tions. Another benefit of integrator feedback is lower noise 
output as the integrator forms an output filter as contrasted 
to pole-zero cancellation which only forms an incomplete 
filter of the input stage. Figures 1 1 and 12 show the relation- 
ship between the frequency and time or transient response of 
a feedback amplifier that employs integrator feedback. 

Figures 13 through 16 illustrate the effect of a pole-zero 
mismatch. A pole-zero mismatch creates a "tail" or a long 
time constant settling term in the transient response. Pole- 
zero compensation is not as effective as integrator feedback 
in stabilizing an amplifier but should be considered as there 
are times when the integrator itself can become unstable. 
Pole-zero compensated amplifiers often have higher slew 
rates. 

The second architecture that will be discussed is known as 



G-- 



1 



+i- 



A(o)p (o,^ A(o) 
1 1 



eon 2 Mon 



o)P I co, + coj 



where con = i/A(o) p co,^ 

CO, + COj 



2VA(o)pco,co 2 



Step Response: 

e (t) = j e,(t) [l - sin (con VT^ t + cos'' q] 



FIGURE 11. Transient Response Integrator Compensation. 




FIGURE 12. Open Loop Gain, Closed Loop Gain, and Tran- 
sient Response Integrator Compensation. 

the folded cascode operational amplifier. This circuit ar- 
rangement is very useful as all the open loop gain is 
achieved in a single stage. Since all of the gain is developed 
in a single stage, higher usable gain bandwidth product will 
result as the Bode Plot will tend to look more like a single 
pole response which implies greater stability. 

Figure 17 shows a simplified schematic of this type of 
amplifier. The input terminals of this amplifier are the bases 
of transistors Qi and Q 2 . The output of transistors Qi and Q 2 
are taken from their respective collectors and applied to the 
emitters of the common base PNPs Q 4 and Q 5 . Transistors 
Q 4 and Q 5 act as cascode devices reducing the impedance at 



© 



R, C, 

H/WH(- 



-OV+ 




-ov 



■In °"- j~Qi <^j— O+lr 




P 1 +Ap 



A(«o). 



A(o) 



2-Pole Amplifier Pole-Zero 
Network 



FIGURE 13. Pole-Zero Compensation in Op Amp. 



1 Ap 

p 1 +AP 



A(«o) 



_A(0L 



1 + ■ 



ill 

For simplicity assume A(o) co„ » toj. 

(•♦*) 



A(co) 



A(o) 

.♦A] (t + J 

CO,/ \ <0o 



If to, • to,' : 



1 AP 



1 + 



P 1 + 



^ + (1 + AP)oJ 



Step Response: 



FIGURE 15. Pole-Zero Transient Response. 




FIGURE 14. Pole-Zero Compensation Bode Plots. 



191 



"Tail" 




! _ e -<1 +Ap )Wo t 



— < , >=T-r^rf 1 - e ~ (1+A,w - 

e IN P 1 + A P 



CO, 



. e -°>,t 



FIGURE 16. Pole-Zero Transient Response and Pole-Zero 
Mismatch. 

the collectors of Qi and Ch while allowing the signal current 
to pass through transistors Q 4 and Q 5 with little attenuation. 
The term "folded cascode" refers to the fact that the PNP 
transistors not only serve as cascoding devices but also 
"fold" the signal down to a load connected to the negative 
power supply. Transistors Q g and Q 9 act as current source 
loads for transistors Q 4 and Q 5 thereby enabling the ampli- 
fier to achieve gains of up to 80 in a single stage. Emitter 
followers drive the output load in a similar manner to the 
method described for the FET operational amplifier. An 
additional benefit of this architecture is that the amplifier 



can be stabilized with a single capacitor thereby approximat- 
ing a single pole response without a settling "tail." 

COMPARATOR 

The comparator is a common element in a signal processing 
system and it is used to sense a level and then generate a 
digital signal, either a "1" or a "0," to report the result of that 
comparison to the rest of the system. Comparators can be 
implemented two different ways, either using a high gain 
amplifier or by using the latching type approach. Each type 
of comparator has advantages as will now be explained. 

When a high gain amplifier is used as a comparator, many 
low gain stages are cascoded to achieve high gain bandwidth 
product. A simplified example of a 20ns comparator is 
shown in Figure 1 8. This is in contrast to the way a wideband 
operational amplifier would be designed. A design objective 
for a wideband operational amplifier would be to achieve 
high gain in a single stage to avoid accumulating an excessive 
amount of phase shift. Feedback will be applied around an 
operational amplifier. It is important to achieve a phase 
characteristic approaching single pole response. Phase shift 
through a comparator is usually not important although high 
bandwidth and low propagation delay is desirable. The 
design of an open loop amplifier and a comparator are 
similar. The main differences are that comparators do not 
have to have stable, or linear, gain characteristics and the 
output is designed to be logic compatible such as TTL or 
ECL. Unlike a linear open loop amplifier, a comparator is 




FIGURE 17. Folded Cascode. 




FIGURE 18. High Speed Comparator. 



v BUS o 




20us 



At t < Power in Q, > 2mW 

Power in Q 2 - 
Att>0 Power in Q, -Q 2 = 1mW 

Due to thermal time constant, temp, of Q, and Q 2 doesn't change quickly. 
ATemp^ = JA A X P = 1 00°C/W X 0.001 W . 0.1 °C 
<JV B 



AV Bl 



dT 



X AT = 2mV/°C X 0.1 °C = 0.1 mV 



FIGURE 19. Thermal Offset. 



designed to operate in a non-linear mode with the output 
saturating at either logic extreme, depending upon whether 
the input signal exceeds the input reference. Additionally, 
care is taken when the intermediate stages are designed to 
ensure excellent overload recovery and minimize propaga- 
tion delay. Each stage of a well-designed comparator is 
designed in much the same fashion as an ECL logic stage in 
the sense that saturation is avoided and maximum interstage 
bandwidth is preserved by using emitter followers to couple 
the signal from stage to stage. 

Comparator oscillation problems can be solved using a 
latching comparator, but both architectures are sensitive to 
the "thermally" induced offset. The thermally induced offset 
is created when the input signal biases the input differential 
amplifier to either being entirely "on" or "off," thereby 
changing the power dissipation of one side of the differential 
pair with respect to the other side. This effect should be 
minimized by reducing the power dissipation of the input 
differential pair. The limit is determined by bandwidth and 
slew rate requirements of the inputs. Figure 19 shows a 
calculation which estimates the amount of thermally induced 
offset in a comparator. This calculation shows that the 
comparator offset will initially be 0. lmV before coming into 
balance at the rate determined by the thermal time constant 
of the system. The thermal time constant of the system is in 



193 



Rg 



^> ^> 



-ov 



82dB 



G-G, XG 2 XG 3 XG 4 = 7X7X7X35» 12,000 -♦ t 
BaVSTAGE = 225MHz 
0SHIFT = 4X45°C-18O°C 




Open 

Loop Gain = Loop 
Gain 



Insertion 
Gain 



70dB - 20 log 



1 



2it Rg f C s 



70dB - 20 log 



' 225MHz 



2ic (300)(225 X 10 6 ) X (0.1 X 10"' 2 ) 

70dB - 27dB = 43dB 

When = 0°, oscillation occurs. 



— 180° 



f(Hz) 



FIGURE 20. Comparator Oscillation. 

the order of lOus to 100|is and is affected by factors such as 
the physical size of the transistor as well as the method by 
which the transistor die is attached to the header. Thermally 
induced offset can become a serious problem in high speed, 
high accuracy systems and can often be the limiting factor 
that determines performance. 

The other effect that limits the accuracy of the non-latched 
comparator is the tendency for oscillations. Comparator 
oscillations are usually due to parasitic feedback from the 
output signal being capacitively coupled back to the 
comparator's input. In discrete form this problem is very 
difficult to solve while still trying to maintain high sensitiv- 
ity and low propagation delay. Figures 20 and 21 show a 
diagram which describes how the parasitic feedback be- 
tween the pins of the package comparator can create enough 
feedback to stimulate an oscillation. Even in hybrid form, 
comparator oscillation is a serious problem. Integrating the 
comparator onto a monolithic chip is beneficial as the planar 
nature of this means of construction will reduce the amount 
of parasitic capacitance. 

As previously mentioned, the other type of comparator that 
is employed is known as the "latching type." Figure 22 
shows a simplified schematic of the front end of this type of 



-o v+ 




Gain* = — , 



re 0.026 0.026 
I 

1 3rd Stage 



V- 



Since the gain is proportional to I, a 43dB gain reduction occurs when: 
I @ Balance 



I @ Unbalance 



.141 



AV RF = 26 In 



I < 



I @ Unbalance 



: 129mV 



Overdrive for43dB gain reduction: 
av be 129 



OVERDRIVE " 



= 375uV 



FIGURE 2 1 . Gain Reduction to Stop Comparator Oscilla- 
tion. 



comparator. The latching comparator develops "high gain" 
by going into a regenerative state when being strobed by the 
latch enable signal. Typically the input pair, Qj and Q 2 , will 
have a gain of at least 10 when the comparator is in the 
"tracking" mode. At the instant of latching the "tail current," 
I, is then switched from the input "linear pair" to input 
"latching pair" Q 3 and Q 4 . The state of the latch will then be 
determined by the state of the signals on the input bases of 
Qi and Q 2 with respect to each other. The latching pair 
receives its feedback through the two emitter followers, Q 7 
and Q 8 . The emitter followers also feed the appropriate logic 
level. While the comparator is held in the latch state it is 
impossible for oscillations to occur as the comparator is 
permanently held in the previous state. If the comparator is 
placed in the low gain state for a short amount of time the 
tendency for oscillation is reduced as: 1) the loop gain is too 
low to support oscillation, and 2) if the strobe time is short 
the state of the latch is already determined before the 
parasitic oscillation is permitted to build up. 

The fastest analog to digital converter is composed of an 
individual latch comparator for each quantizing level. The 
design of this type of converter would not be practical by 
any other technique as only the latching comparator offers 
sufficient simplicity to allow for the necessary amount of 
integration. More detail about "flash converters" will be 



given later. GaAs is an emerging, exceptionally high speed 
technology; while being able to achieve high speed, it does 
so at the expense of low gain. The latching comparator is 
extremely useful here, as it would not be practical to achieve 
the comparator function in this technology any other way. 

TRACK AND HOLDS 

One of the most important elements of a data conversion 
system is the track and hold. Track and holds and sample and 
holds are very similar and for all practical purposes are 
identical. If the track and hold or sample and hold command 
is direct coupled, the two types of samplers are identical. 
Some types of extremely fast samplers have their sample 
command AC coupled and for a short period of time the 
signal is "sampled" and then held; hence the name "sample 
and hold" was coined. Before a description of many track 
and hold architectures are given it will be appropriate to 
explain why track and holds generally precede an analog to 
digital converter. 

A track and hold is used to reduce the aperture time of the 
sampling system. (A sampling system would be a track and 
hold driving an analog to digital converter.) In general it is 
necessary for the input signal to the analog to digital con- 
verter to be constant during the conversion process to avoid 




FIGURE 22. Latch Comparator Front End. 



195 



EFS 

e(t) = — — sin2icft 

EFS = Full Scale ADC Range 



^- ( EFS*oosa«ft,^a-fEFSK 
at at 

de(t) 
dt 



EFStc 



Assume maximum allowable change during ADC conversion time. 
T = 1/2LSB and EFS = 2TSB where N is the number of bit ADC. 



f. 



1/2LSB 



T 2 N LSB 7t JC 2 |N "»T 
As an example, let N = 1 2 and T = 1 us: 
1/2LSB 



-■ 38.9Hz 



T 2 N LSB it 

With a sample/hold, the maximum frequency would be 500kHz. 



FIGURE 23. Maximum Input Frequency for ADC Without 
a Sample/Hold. 



e OUT 



T/H 



' e OUT 











Fourie 


r Transfo 


rm of Output 



fs 



E (f)-|vei 2,rt, dt--j^ r (ei 2,t «)| 



_y_ ei^-i ve 1 *"" (e j,lfT - e" iltfT ) 
irf 2j la 2j 



Ve )irfT 



sinicfT 



T 



E o (f) _ c «n- sin«fT U {ms) \ 

E (o) "* «rr r I 
/ 

Phase 



sin ji — 
fs 



FIGURE 24. Track/Hold Bandwidth. 



error. A successive approximation ADC uses an N-step 
algorithm when forming the conversion and if the signal 
varies during the conversion process the wrong approxima- 
tion would take place. Even flash converters can benefit 
from being driven from a track and hold since the time 
delays of all the comparators are not identical. Figure 23 
calculates the improvement in ADC performance that can be 
obtained when a track and hold precedes an ADC. Figure 23 
shows that the maximum frequency that can be processed by 
a lu.s ADC would be only 38.9Hz. When a sample and hold 
drives the ADC the maximum frequency would rise to the 
Nyquist rate of 500kHz. Additionally, applications will be 
shown of how track and holds can be used to "deglitch" 
DACs and how a peak detector can be formed. Many track 
and hold architectures will be presented with a discussion of 
the strengths and weaknesses of each type. The discussion 
will show how the characteristics of the sample and hold 
interact to gain an understanding of how to optimize the 
design for particular applications. This will also be a useful 
way of understanding the increasing level of complexity. 
Before the comparison of different types of architectures 
begins, Figure 24 calculates the bandwidth of a track and 
hold and Figure 25 shows a plot of the frequency response. 

As a way of introduction, the most elementary track and 
hold is shown in Figure 26. A FET switch is connected to a 
capacitor which in turn is isolated from the output by a high 
input-impedance buffer. When the sampling signal, which is 
connected to the gate of the N-channel enhancement mode 
FET, is in the high state, the FET series resistance is at its 
lowest which is R 0N . During this condition the output of the 
buffer is the input signal modified by the low pass filter 
action of Rqn and the holding capacitor C. The voltage 
across the holding capacitor will follow the input voltage 
until the gating signal is returned to the low state and the 
FET is turned off. At that point the holding capacitor retains 
the input voltage at the instant of sampling. Figure 27 shows 
waveforms that depict the dynamic characteristics of the 
track and hold. When the track and hold is driving an analog 
to digital converter, the held voltage is then converted to its 
digital equivalent. The circuit previously described has lim- 
ited capability. To determine the nature of the limitations, a 
design example will show how the performance is deter- 
mined. For this design example a typical N-channel D-MOS 
FET will be used along with a FET op amp connected as a 
voltage follower. The FET has the following characteristics: 

h Ron = 5012 

2. V T = 2.5V 

3. Cg D = 0.5pF 

4. C DS = 0.1pF 

5. I DSS = 25mA 

6. I OFF = 50pA 

Assume for this example that the input signal range is 10V 
peak to peak and it is tolerable that each error source can 
contribute ±0.01% of Vjn to the overall error. Particular 



oats 



A(f) 



G~ -3.9dB 




fs/2 fs 



|A(f)l = 



Frequency 



sinjt — 
fs_ 

4 



FIGURE 25. Frequency Response of Sample/Hold. 



- Input Signal 

. Track/Hold Output 




\ 

Sampling Signal 



FIGURE 27. Track/Holds Wave Forms. 



+5 

V«<n_j-r 



x 




-ov n 



6 

Sampling 



On 10V 



-Off -7.5V 



FIGURE 26. Basic Sample/Hold. 

applications may assign the value of individual error sources 
differently. The sources of error that will be considered are: 

1. Change induced offset error 

2. Aperture non-linearity 

3. Signal feedthrough 

4. Aperture jitter 

5. Aperture delay 

6. Droop 

7. Acquisition time 

8. Track to hold settling 

9. Full power bandwidth 

CHARGE INDUCED OFFSET OR 
PEDESTAL ERROR 

To ensure that the FET is turned on with a low resistance it 
is necessary to exceed the peak input signal by 5V. There- 
fore the voltage applied to the gate of the FET is 

Von + V PEAK = 5 + 5 = 10V 

To ensure that the FET is off it is necessary that the FET is 
reverse biased under the worst case conditions. The mini- 
mum voltage that the sample and hold has to process is -5V 
and it is desirable to reverse bias the gate to source under 



s D 



_r~u— r 




-ov 



ON 
V FF 



_TL 

Error = V IN X 0.01 % - 1 0V X 0.01 % = 1 mV 



S D 

Vqate T 

— I 1 7.5 




-ov Q 



jr-rc: 



Track 



T 

Track 



Hold 



Vqffset = ^T-^T- X W. if C GD - 0.5pF 
° + °gd c _ o.009uF 



"offset 1 



0.5X1Q- 12 
0.009 X 10" 6 



X17.5-1mV 



FIGURE 28. Charge Induced Error. 



these conditions so the off signal that is applied to the gate 
of the FET is -7.5V. See Figure 26. The total signal swing 
that is applied to the gate of the FET is therefore 17.5V, the 
sum of the on and off signals. Figure 28 shows how a voltage 
divider is formed by the gate to drain capacitance C GD and 
the holding capacitor C. A charge induced offset error is 



197 



On 



Off 



T * 

v G 

n 




-OV 



v IN o — M/^ 



T 
X 



c, 




-ov 



Small Signal Bandwidth 



2k R on C 

1 



2it(50) 0.009 XKT 6 
: 354kHz 



FIGURE 29. S/H Frequency Response. 

then created by this voltage divider action and its value is 
given by: 



^OFFSET - V G ATE 



/_Cop_J| 

\c + c GD / 



Therefore, to reduce the charge induced offset error to: 

0.01% x 10 = lmV 
requires a holding capacitor of: 

Qjd * v gate - C G d * v offset 



C = 



'OFF 



c 0.5pF- 17.5V -0.5pF. lmV = g ^ 
lmV 

Now since the value of the holding capacitor (C H = C) is 
determined, the track and hold bandwidth would be (see 
Figure 29): 

BW = 1/2jc(R on )(C h ) = 1/2ji(50)(9 x 10-9) 
= 354kHz 



APERTURE INDUCED NON-LINEARITY 

In the previous discussion on charge induced offset error it 
was assumed that the gate turn off signal was always 17.5V. 
If the input signal were sampled at its peak of 5V and the 
FET threshold voltage were 2.5V, the FET would stop 
conducting when the voltage on the gate was 7.5V. The 
effective gate signal swing would be reduced to 15V and the 
amount of charge induced offset would also be reduced. 



T "1 



r 

1 7.5 




-ov Q 



-5V 

m°— i_r 



X s :X c H 



r 

I 7.5 



15X0.5X1Q- 12 
0.009 X10- 6 
. 0.83mV 



-ov 




5X0.5X10-' 2 



0.009 X10" 6 
= 0.28mV 



Vt - 2.5 



FIGURE 30. FET Threshold Characteristics and Aperture 
Non-linearity. 



Similarly, if the input signal being sampled is at the mini- 
mum level of -5V, the effective gate swing would be 5 V. In 
the previous section it was calculated that if the gate swing 
were 17.5V, the charge induced offset would be lmV. See 
Figure 30. Actually the charge induced offset is modulated 
by the signal and varies between 0.83mV for the positive 
extreme and 0.28mV for the negative extreme. Since both 
offsets are less than the allowable error this is not a problem; 
the holding capacitor is relatively large. As will be seen 
later, this will not always be the case when it is desirable to 
achieve wider band operation. This effect will be considered 
again for wider band designs when it could become a serious 
source of error. 



SIGNAL FEEDTHROUGH 

Signal feedthrough occurs because of the presence of a 
capacitor that is connected from the drain to the source of the 
FET. This is a parasitic capacitor that is either due to layout 
or other stray effects. Referring to Figure 31, it is seen that 
the input signal will be coupled to the hold capacitor and is 
given by: 

Vfeedthrough = (C D s/C H )(V IN ) = (0.1pF/0.009jiF)(10) 
= llluVp-p 

which is a tolerable error. Again it will be seen that wider 




FIGURE 31. Signal Feedthrough. 



bandwidth designs that must resort to smaller holding ca- 
pacitors will not able to meet this specification as easily. 

APERTURE JITTER 

Aperture jitter or uncertainty is the variation in the time 
when the sample and hold switch opens after a sample and 
hold transition occurs, or the time variation in the aperture 
delay. (Aperture delay is the elapsed time from the activa- 
tion of the sample to hold command to the opening of the 
switch in the hold mode.) There are two sources of aperture 
jitter: power supply induced noise and threshold variation 
due to thermal noise. If attention is paid to filtering the 
power supply properly, as well as using a well-regulated 
power supply, this will not be a source of aperture jitter. As 
a practical matter, because of measurement difficulty, deter- 
mining the amount of aperture jitter that is present in the 
system is often more of a problem than limiting it to an 
acceptable level. Techniques for measuring aperture jitter 
will be shown in the measurement section. Assume that the 
noise associated with the logic threshold is 50nV/VHz. This 
would be ten times greater than the noise of a typical linear 
amplifier. Further assume that the bandwidth of the logic 
circuit that develops the gate signal is 300MHz. The noise 
variation of the logic level would then be (see Figure 32): 

Threshold variation due to logic noise = (50nV)(V300E6) 
= 0.87mV 

If the logic signal rate of transition were 0.4V/ns, the 
aperture jitter would be (see Figure 33): 

Aperture jitter = (threshold noise)/(logic slew rate) = t A 
= (0.87m V)/(0.4V/ns) = 2.2ps 

which will be seen to be negligible for all but the highest 
sampling rate data conversion applications. Aperture jitter 
can create amplitude noise by causing a variation of the 
sampling point of dynamic signals. The noise can be pre- 
dicted by: 




Logic Noise = Noise X VIw 
Density 



= -2°2Y_ X V300X10 6 = 0.87mV 
VHz 



FIGURE 32. Logic Noise. 




/ Threshold 
/ Variation 


Logic A A A A A A fx I 
Input v V w v v y\J 

Logic / / 
Output 




Aperture Jitter = 


Threshold Noise 


Logic Rate of Change 


= 


087mV =2.2 P S 
0.4V/ns 



FIGURE 33. Aperture Jitter. 



Aperture induced noise 
= (signal rate of change)(aperture jitter) 
= (de/dt)(t A ) 
= (FS)(TC)(f)(t A ) 

Assume a 12-bit ADC with a sampling rate of 20MHz. 
FS = 4096LSB, f = 10MHz, t A = 2.2ps. 

Aperture induced noise = (4096)(7t)(tA) 
= (4096)(JI)(10E6)(2.2E-12) = 0.28LSB 



199 



0.28LSB aperture induced noise would be acceptable for a 
12-bit ADC with a Nyquist rate of 10MHz. Figures 34 and 
35 illustrate this effect. 



each other. Figure 37 shows a circuit diagram of a FET 
driver circuit that is TTL compatible and is suitable for 
driving the sample switch. 



APERTURE DELAY 

The aperture delay is the elapsed time from the activation of 
the sample to hold command to the opening of the switch in 
the hold mode. See Figure 36. Controlling aperture delay is 
important when multiple channels need to be matched to 




FIGURE 34. Aperture Induced Noise. 



Input 




Sampling 



Output 



■*- Aperture Jitter 



Range of Outputs 
Due to Aperture 
Jitter 



Aperture Induced Noise = Signal Rate of Change • Aperture Time 



= E FS • k • f • t a 

= 4096 • it • 10 X 10 6 • 2.2 X 10~ 12 = 0.28LSB 



Fort = 10MHz 

E FS = 2 12 -t a = 2.2ps 



DROOP 

While the sample and hold is in the hold mode the leakage 
current that flows through the FET and the input bias current 
of the operational amplifier will tend to discharge (or charge) 
the holding capacitor. Both sources of current are about 
50pA at 25°C so the capacitor will change at a rate of (see 
Figure 38): 

I/C = 100pA/0.009uF = 0.01 lV/s 

If the sample and hold were driving an ADC with a 10(i.s 
conversion time, the held value would change by O.llixV 
during the conversion process. Since the allowable error 
from each source is lmV, this is not a source of error at room 
temperature. Since leakage current doubles every 10°C, 
when the operating temperature increases to 125°C, the 
voltage change, due to droop, during the conversion would 
increase to 0. 1 lmV, which is still below the allowable value. 
Wider band designs that use smaller holding capacitors will 
not meet this specification as easily and other methods will 
be shown that can reduce the droop to acceptable levels. 

ACQUISITION TIME 

The calculation of acquisition time of a sample and hold is 
identical to the way settling time is determined for an 
operational amplifier. (It is really the same phenomenon.) 
The sample and hold will slew in response to a large signal 
change until the output rate of change of the sample and hold 




Input to Sample/Hold 




Input to Switch Driver 



Gate Signal 



Aperture Delay 



FIGURE 35. Aperture Induced Noise. 



FIGURE 36. Aperture Delay. 




X7 




FIGURE 37. FET Switch Driver. 



v, N o — i | - 



^ c 



In + U — 




S/H Output 




Sample Pulse 



.±.JdUo = 50pA + 50pA 
C C 0.009UF u.u pv/pb 



Droop Rate 



FIGURE 38. Droop. 



settling, the linear part of the settling is given by the formula 
(see Figure 41): 

V = V(l -c-< 1/Ron ' Ch) ) 

Rearranging: 

t = (RqnXCh) ln(V/0.001) 
t = (0.45ns) ln( 1.25/0.001) = 3.2|is 

The acquisition time of the sample and hold is then the sum 
of the time spent during slewing and the time spent during 
linear settling, or: 

Acquisition time = 3.1p.s + 3.2(is = 6.3|is 

It has been assumed that the settling time of the buffer or 
operational amplifier that the holding capacitor drives is 
much smaller than the above number of 6.3|is. In fact, it is 
possible to get monolithic FET amplifiers with settling times 
under l|is, which will increase the above acquisition time by 
perhaps 3%. 



is within its linear capability. When is large enough to 
pinch off the FET, the slew rate of the sample switch is given 
by (see Figure 39): 

Slew rate = l DSS /C H = 25mA/0.009uF = 2.8V/ns 

The sample and hold will slew until the remaining output 
change is within the linear capability of the sample and hold 
(see Figure 40): 

V = (RqnXIdss) = 1-25V 
For a 10V input change the sample and hold will slew until 
the output is within 10V - 1.25V = 8.75V of its final value 
which will take (8.75V)/(2.8V-ns) = 3.1p.s. The remainder 
of the acquisition time occurs as the remaining 1.25 V has to 
settle to within 1 mV of the final value. Assuming single pole 



TRACK TO HOLD SETTLING 

Track to hold settling is the time that the sample and hold 
takes to recover from the gate transient that is coupled on to 
the hold capacitor and the settling time of the buffer that 
isolates the hold capacitor from the output. The sample and 
hold that is being designed has a large enough hold capacitor 
so that track to hold settling is not an important factor for 
this sample and hold. Another example will better illustrate 
track to hold settling. 

FULL POWER BANDWIDTH 

The full power bandwidth of a sample and hold is calculated 
in the same manner as it is for an operational amplifier. 



201 




FIGURE 39. Capacitor Charged from a Constant Current. 




1 



Linear Settling 



Slew Time 



Slew Rate = 



'dss 25X10" 3 



0.009 X10" 6 



2.8V/(js 



Linear Response 



When de/dt = Slew Rate, response follows exponential: 



In 



R ON C 



= 25X10^X50 = 1.25V 



FIGURE 40. Acquisition Time. 



Slew Time - „ 1 / 25> = 3.1ms 
2.8V/|js 

Linear: 

1.249=1.25 (l-e- |/ ( 50 >( a009X10 " s ) 

1.25 
0.001 



t = (50) (0.009X10^) In 



. 3.2US 



Acquisition Time = Slew Time + Linear 
= 3.1 + 3.2 ■ 6.3us 



FIGURE 41. Acquisition Time. 




V 0UT = 5 sin 2jc ft 



I = | = 5.2 



Max 



Max 



,. ^^1 = iiyilL =8 9.1KHz 
(5) 12k) 1 0)t 



FIGURE 42. Full Power Bandwidth. 

Knowing the full power bandwidth is important as it is 
necessary to operate at less than that frequency to maintain 
low levels of distortion. For the design example in question 
(see Figure 42): 

v out = (5) sin(27tfT) and: 
dV 0UT /dT = Max Slew Rate = 10(7t)f 

Rearranging terms: 

Full Power Bandwidth = (Slew Rate)/10(7t) = 89.1kHz 

The above example demonstrates how to approach the 
design of the simplest type of track and hold. Even though 
it is simple, it would be very useful as the full power 
bandwidth of 89.1kHz would be adequate for processing 
audio signals. A sample and hold with an acquisition time of 
6.2(ls driving an ADC with a 10|J.s conversion time would 
have an adequate sampling rate to process an audio signal. 
Furthermore, this circuit could be built for a cost in the $5- 
10 range. While the design of this circuit is relatively 
straightforward, it does have limited bandwidth. Several 




FIGURE 43. Balanced Track/Hold. 

more examples of track and hold designs will be given 
showing how substantial increases in bandwidth can be 
made without sacrificing much in the way of linearity. 

Assume for the purposes of this example that it is necessary 
to reduce the acquisition time of the sample and hold to 
300ns. This would be about a twenty-fold decrease com- 
pared to the previous sample and hold that was designed. 
From the reference point of the previous example the hold- 
ing capacitor would have to be reduced by a factor of twenty 
to reduce the acquisition time from 6.2s to 0.3s. If that were 
done, both the aperture induced linearity and the droop 
would increase by that same factor. Neither is desirable, as 
the goal of this new design is to achieve +0.01% linearity. 
Figure 43 shows a simplified circuit diagram of a sample and 



hold which is capable of faster operation while still main- 
taining good linearity. The track and hold shown in Figure 
43 is faster due to the balanced connection of matched FETs 
Qi and Q 2 . When this track and hold makes the transition 
from the track to the hold mode, the gate to drain capacitance 
and the hold capacitor associated with each FET form a 
differential connection, thereby eliminating the charge in- 
duced offset or pedestal error. Figure 44 illustrates this fact. 
This circuit then becomes sensitive to how well Q and C 2 
are matched as well as the C RSS of the FETs. Analysis shows 
that the charge induced offset error is given by: 

v 0FF = v G .^ 



/AC RSS | AC \ 
V C RSS + C / 



= 17.5 (0.5/450) (0.05 + 0.05) = 1.9mV 

The sample and hold with the balanced hold capacitor 
arrangement does not quite meet the goal of a 1 .OmV error. 
Now it remains to be seen what the settling time of this 
configuration will be. As previously shown, the linearity 
goal of ±0.01% will be met as the effective voltage swing is 
not as large as shown in the calculation of Vqff- Since the 
acquisition time is directly proportional to the holding ca- 
pacitor, the acquisition time of this faster sample and hold 
will be 300ns. Once the settling time becomes that fast, other 
factors that we previously neglected must now be taken into 
consideration. Monolithic FET op amps are just now becom- 
ing available with 300ns settling times so that the calculation 
of the acquisition time of this architecture must be increased. 
A good approximation to estimate the combined acquisition 
time would be to "RMS" the individual settling times. The 
acquisition time when measured at the output of the opera- 
tional amplifier would be 424ns. When performing this 




~T~CT 

XT 




o 

Vqate 



', C RSS / AC RSS AC 



5 I -^-l (0 



FIGURE 44. Capacitance Mismatch. 



203 



calculation for the example in question, a subtlety about 
acquisition time should be pointed out. The previous two 
architectures that have been discussed are ones where the 
sample and hold function is separate from the associated 
buffer or op amp. This is not true for a feedback architecture 
that will be discussed later. In some systems applications the 
distinction between the voltage developed across the hold 
capacitor and the output of the buffer are important. One 
important application that will be discussed in detail in the 
section on analog to digital converters is where the sample 
and hold drives a sub-ranging ADC. Even though the input 
signal must be acquired accurately, the voltage does not 
need to be accurately known to begin the conversion pro- 
cess. Figure 45 shows how the hold capacitor acquires the 
signal in 300ns while the output of the buffer reaches the 
same point in 424ns. 

One of the drawbacks of this and the previously described 
circuit is the charge injection of the gate signal through the 
source to gate capacitance as shown in Figure 44. The nature 
of the driving impedance can create a great deal of uncer- 
tainty as to the nature of the pedestal during the time when 
the FET is being switched from on to off. The source may 
be ringing or settling in some unfavorable manner and the 
track and hold will store the results of the driving source not 
settling. The track and hold would then benefit from being 
driven from a buffer to eliminate this problem. 

Another problem with the circuit shown in Figure 43 is the 
poor feedthrough performance. If the feedthrough capaci- 
tance is 0.1 pF and the hold capacitance is 450pF, the 
feedthrough voltage could be as much as (10)(0. 1/450) = 
2.2mV which exceeds the goal of lmV. To reduce the 
feedthrough voltage, the holding capacitor would have to be 
increased to 990pF. Increasing the hold capacitor to 990pF 
to reduce the feedthrough voltage would increase the acqui- 
sition time across the hold capacitor to 600ns. 

This previous calculation shows how the various design 
parameters can interact and even though one specification is 
met other specifications must be re-evaluated before the 
design is complete. It has been shown that even though the 
arbitrary design goal of 300ns could not be met, this circuit 
should not be discarded, as improved performance has been 
achieved. The cost of this sample and hold is relatively 
modest and could be produced for about $10-15. As a 
practical matter, a sub-500ns sample and hold can be very 
useful when interfacing with a 5u.s ADC and it is desirable 
to minimize the overall conversion time. 

Let us return to the original design challenge, which was to 
design a sub-300ns sample and hold. Another architecture 
that is worth considering is shown in Figure 46. This 
architecture employs the switching FET in the summing 
junction of an inverting feedback amplifier. The advantage 
of this connection is that it is possible to drive the FET with 
a much smaller gate signal which allows the holding capaci- 
tor to become smaller. This architecture also has the com- 
pensating FET connected in a differential fashion so the 
circuit is only sensitive to the match of the FETs and is not 




FIGURE 45. Difference in Acquisition Time Between 
Buffer and Hold Cap. 



sensitive to the absolute value of C RSS . Notice the clamping 
diodes that are placed at the summing junction. These diodes 
reduce the signal that the FETs have to hold off when the 
sample and hold is in the hold mode, thereby minimizing the 
magnitude of the drive signal that needs to be applied to the 
FET. Circuitry to minimize the feedthrough problem could 
have also been applied to the previous two design examples, 
although it would have been much more complicated than 
the two diodes connected to the feedback track and hold. 
The gate drive signal can be made smaller since the switch 
is located in the summing junction of the operational ampli- 
fier and the feedback action of the amplifier tends to drive 
the signal at the summing junction to zero. This also has the 
effect of linearizing the operation of the track and hold since 
the charge induced offset pedestal is not signal dependent as 
it is in the original designs. To ensure that the FET is on, a 
5V signal is applied during the sample or track mode and to 
ensure that the FET is off during the hold mode, a -2.5V 
level needs to be applied. Therefore the total gate swing will 
be 7.5V. 

Since diodes have been placed at the summing junction, the 
maximum voltage that can be developed at the input to the 
FETs is 0.6V peak. From the previous example it was found 
that it was necessary to have a 500pF holding capacitor to 
reduce the feedthrough voltage to an acceptable level. Since 
the feedback track and hold reduces the effective input 
voltage to the FET to 0.6V, the holding capacitor can be 
reduced to 60pF. The effective small-signal time constant 
for this track and hold connection is T = (2R ON + R F )C. 



V, n O AV- 



c, 



1 ^ 



r— WV^ 

R/2 



Sampling Signal 
(a) 




-0V 




V IN vW 



ov 



t = (2R 0N + R)C 
(b) 



FIGURE 46. Inverting Sample/Hold. 



Amplifier will slew until slew rate = -=- 



T = (2 Rqn + R F ) C = (2 X 50 + 300) 60pF = 24ns 



?nnv 

E- Tx Slew Rate = 24 x 10"» X -4.8V 
10" 6 



Acquisition Time - i?^"*,, ^ + Tln-=^— 
Slew Rate Error 

10-4.8 „. , 4V 
+ 24ns In ■ 



200V/US 0.001V 
= 26ns + 203ns = 229ns 



Feedthrough 
y Capacitance 



0.1 pF 
60pF 



Input Clamped by Diode 



Feedback 
Capacitance 



FIGURE 47. Performance of Feedback Track/Hold. 



Assume that the previously mentioned FET was used along 
with a monolithic amplifier with a 200V/ii.s slew rate and a 
30MHz small signal bandwidth. Let R F be 300Q. The 
amplifier will then slew until the remaining voltage change 
is within the linear slew rate capability of the op amp. The 
small signal time constant of this track and hold is then: 

T = [(2)50 + 300][60] = 24ns 

This corresponds to a small-signal bandwidth of 6.6MHz so 
the small-signal bandwidth of the track and hold will be 
determined by the external components rather than by the op 
amp. Therefore, when the remaining voltage that the track 
and hold has to change is 4.8V, the track and hold will cease 
to slew. The time consumed in slewing is then (10 - 4.8)/ 
(200V/us) = 26ns. (See Figures 40 and 41 for a view of the 
acquisition time calculation.) The remaining time is given 
by (24) ln(4.8/0.001%) = 203ns; therefore the acquisition of 
the track and hold is 229ns and the goal of 300ns can be met 
with the architecture shown in Figure 46. Figure 47 summa- 
rizes the performance of the feedback track and hold. While 
this track and hold configuration is able to achieve a lower 



205 




FIGURE 48. Very High Speed Sample/Hold. 



acquisition time, it does so at the expense of a lower input 
impedance. This may not be much of a penalty as the input 
impedance of 300Q is within the capability of many op amps 
to drive with +5V input. 

The last track and hold that will be described is capable of 
acquisition times that are about an order of magnitude faster 
than the last one that was described. This track and hold, 
shown in Figure 48, shares some of the architectural features 
of the previously described ones, although the sampling 
element is different. This higher speed sample and hold uses 
hot carrier diodes in a bridge configuration to form the 
sampling element. Diodes, while more complex to form a 
sample and hold, achieve high sampling speed due to the 
lower time constant compared to a FET and lower threshold 
voltages. As an example, a hot carrier diode operated at 5mA 
has a resistance of 5Q, V D of 0.6V and a capacitance of 5pF. 
Figure 48 shows a diagram of a sample and hold that has an 
acquisition time of 40ns to +0.02% for a 2V step input. This 
sample and hold has a measured aperture time of under 3ps. 
(A technique to measure aperture time is shown in the 
measurement section.) The sampling function is performed 
by switching the bridge of hot carrier diodes CR, through 



CR 4 from the "on" to the "off' state. During the sample 
mode the current I is steered through the diode bridge by 
turning on transistors Q 2 through Q 4 . The bridge is returned 
to the hold mode by turning Q 3 and Q 4 off and turning 
and Q 3 on. The action of turning Q, and Q 3 on creates a 
negative bias on CR, and CR4. Since these bias voltages are 
referenced to the output, creating "bootstrap effect," the 
reverse bias voltage that diodes CR] through CR 4 experience 
becomes independent of signal level. This is an important 
aspect of the design as this action prevents the charge offset 
pedestal from becoming a non-linear function of signal 
level. An ECL signal is coupled to switching transistors Qj 
through Q 4 . The hold capacitor is isolated from the output by 
the type of high speed buffers and op amps described in the 
amplifier section. The sampling bridge is isolated from the 
analog input signal by a high speed open loop buffer. 

As a means of comparison, calculations will demonstrate the 
different performance parameters of this track and hold. As 
will be seen from the calculations below, the diode bridge 
will not achieve as accurate performance as compared to the 
FET designs. 



V,mO 



v+ 

o 



.© "4- 




-ov 



^ c, 



w v ( C M- C D2> 2(0.025) 4 . „ 
V ff = V g X g 1.3mV 



much as a 50ps mismatch between the complementary 
signals that switch the bridge. This translates to an offset 
voltage of (see Figure 50, assume a bridge current of 1 or 
5mA): 

V OFF = I(T/C) = 5mA (50ps/40pF) = 6.3mV 

This effect is also largely independent of signal level due to 
the bootstrapping. 

TRACK TO HOLD SETTLING 

Track to hold settling is a measure of the recovery time of 
the track and hold in response to the track and hold going 
into the hold mode. The previous three architectures are 
dependent upon the sampling element, whether it is a FET 
or a diode, to switch exactly with identical waveform shape 
and turn-off characteristics. In general this will not happen 
and a small signal will be injected into the buffer op amp. 
Track to hold settling is a complex calculation and represen- 
tative waveshapes are shown in Figure 51. 



FIGURE 49. Pedestal for Diode Bridge. 

CHARGE INDUCED PEDESTAL ERROR 

To ensure that the diode bridge is always off, the diode 
bridge is driven by a complementary signal at the top and 
bottom of the bridge. The charge induced pedestal error is 
principally due to the diode capacitance mismatch and is 
driven by (see Figure 49): 

Voff = (VqffXCdi - C D2 )/C 
With care diodes can be matched to 0.025pF. (In actual 
practice means are provided to adjust the capacitance to this 
level and once the adjustment is performed the difference in 
diode capacitance can be held to 0.025pF.) For proper 
dynamic operation V G = 2V and the holding capacitor is 
40pF. Substituting into the above equation yields: 

Voff = (2)(0.025/40) = 1.3mV 

Unlike the FET designs, this is strictly an offset error as the 
bootstrapping action renders this offset voltage independent 
of signal level. 

SWITCH DELAY PEDESTAL ERROR 

The diode bridge switching arrangement has an additional 
source of error that is not possessed by the FET switch. If the 
current sources that bias the bridge are not symmetrically 
switched, the hold capacitor will start to discharge until the 
other current source is switched. This error manifests itself 
at the system level as if it were an offset voltage. To a first 
approximation the cross-coupling eliminates the time mis- 
matching that exists between the NPN and PNP switching 
pairs. However, due to second order effects as a result of 
different levels of parasitic capacitances, there is typically as 



v+ 




_ 5X10-3X50X10-' g 
40X10" 12 

= 6.3mV 



FIGURE 50. Switch Delay. 



207 





'out 



Vour^Ve-^c 



Track to Hold 
Settling 



~L 





-ov„ 



H h- 



I I Track to I 



)Hold 



FIGURE 51. Track to Hold Settling. 
SIGNAL FEEDTHROUGH 

When in the off state, the top and bottom of the bridge are 
clamped by a low impedance, thereby preventing any signal 
coupling through that path. Signal feedthrough does occur 
due to layout and with care a coupling capacitance of O.OlpF 
can be achieved between the input and output of the bridge. 
This would yield a feedthrough level of (Figure 52 shows the 
bridge in the off state): 

^FEEDTHROUGH = V 1N (Cc/C) = 2(0.01/40) = 0.5mV 

APERTURE JITTER AND DELAY 

Aperture jitter of less than 3ps can be achieved and aperture 
delay of 3ns is also achievable. The lower aperture delay is 
due to the interface circuitry being wideband ECL. 

DROOP 

The leakage current that can be achieved with a pair of 
matched hot carrier diodes is much higher compared to the 
current levels that can be attained with FETs. Leakage 
current of InA can be achieved with proper thermal level 
layout. The droop will then be: 

Droop = lnA/40pF = 25^V/ns at 25°C, 
or about 25mV/u,s at 125°C 




FIGURE 52. Bridge in Off State. 



ANU l-ULL KUWbK BANDWIDTH 

To complete the comparison a calculation will be made of 
the acquisition time and the full power bandwidth using 
methods previously demonstrated. The fastest sample and 
hold is designed to handle only a 2V waveform so the 
equivalent 0.01% error is 0.2mV. Assume that the amplifier 
bandwidth is 80MHz with a slew rate of 300V/u.s. Figure 53 
shows this calculation. 

As previously mentioned, one of the most common applica- 
tions for a track and hold is to precede an analog to digital 
converter for purposes of reducing the aperture time. To- 
wards the end of the section on digital to analog converters 
another application will be shown on how a track and hold 
can be used to "deglitch" a DAC. A third application is how 
a track and hold can be used to make a precise peak detector. 
Figure 54 shows the block diagram of a peak detector. The 



Amplifier will slew until slew rate « ■ 



1 



. 1 .99ns 



2jtBo> 2ti80X10 6 
E - T • Slew Rate = 1 .99 X 10"* • 300V/ps = 0.6V 



Acquisition Time = 



Input - E 
Slew Rate 

2-0.6 



+ Tln 



Error 



+ 1.99ns In 



0.6 



300V/ps 0.0002 
. 4.7ns + 15.9ns - 20.6ns 



Full Power Bandwidth = 



Slew Rate 
(V PEAK )(27t) 

300V/ps 
(D(2«) 



. 47.7MHz 



FIGURE 53. Acquisition Time and Full Power Bandwidth 
Calculation for High Speed Sample/Hold. 



locating the point in time where the peak occurs. The output 
of the comparator allows the track and hold to track the 
signal until the peak is located. Once the peak occurs the 
comparator reverses state thereby placing the track and hold 
in the hold mode, which stores the peak amplitude for 
further processing. 

DIGITAL-TO-ANALOG CONVERTERS 

The schematic shown in Figure 56 is typical of the architec- 
ture of a high speed digital to analog converter. The digital 
to analog converter shown in Figure 56 is ECL compatible 
but shares many of the same elements of TTL compatible 
DACs as the core current steering mechanism is similar. 
Most recently, CMOS technology has been used to design 
high performance digital to analog converters. CMOS DACs 
have been designed with 12-bit resolution but have not been 
able to achieve the speeds that can be achieved with bipolar 
technology. Recently GaAs technology has been used to 
design exceptionally high speed DACs, with settling times 
in the Ins vicinity, and in some ways are similar in topology 
to the way a bipolar design would be approached. Therefore, 
describing the design considerations for a high speed digital 
to analog converter implemented with bipolar technology 
will serve as a means to understand the design consider- 
ations for a high speed, high resolution DAC. Along with the 
high speed switch, other elements such as the "servo amp" 
and reference circuitry are also representative of other high 
precision digital to analog converters ranging in settling 
times down to 5ns and resolutions to 16 bits. The particular 
DAC that will be described has 12 bits of resolution with a 
settling time to ±0.01% accuracy in 25ns and is capable of 
operating over the temperature range from -55°C to +125°C. 
This converter is representative of what can be achieved 
with modem monolithic processing. The DAC is built on a 
20V process that contains 1GHz NPNs along with compat- 
ible thin film resistors. As will be described later, the thin 
film resistors are laser-trimmed to achieve true 12-bit linear- 



v, N o- 



Track/Hold 
T/H Gate 



OFFSET 

~®-u 



Delay Line J — 




) V OUT 



Comparator 




FIGURE 54. Peak Detector. 



209 



'out 'out 
O O 



Bit 1 



Bit 2 





Bit 4 



Bit 11 



Bit 12 



5mA 




2.5mA 




1.25mA 





















-ov„ 



9.8uA 




4.9mA 




c 













FIGURE 55. Binarily Weighted Current Source DAC. 

ity over a very wide temperature range. Furthermore, the 
thin film resistors are capable of maintaining their accuracy 
over long periods of time and represent a reliable technique 
for producing a high speed, high resolution, low cost digital 
to analog converter. The converter that will be described is 
entirely monolithic as it contains the precision current 
switches, servo amp, and low drift references. Only a few 
capacitors that are too large to be integrated and are needed 
for filtering and bypassing are left off of the chip. 

The converter consists of twelve switches that are driven in 
a non-saturating manner. In order to steer the current as fast 
as possible through the output switch, it is very important to 
pay careful attention to avoid saturation; once a transistor 
saturates, the recovery time can easily increase by a factor of 
twenty or more. There are many ways to approach the design 
of this kind of a DAC. The detailed design considerations 
will be described, but before that explanation will be given, 
an overview of different DAC architectures is offered. One 
method would be to binarily weight the individual bit switches 
and then sum the outputs as shown in Figure 55. High 
accuracy can not be achieved using this method as it is 
difficult to accurately match the separate current sources and 
switches over such a wide range of currents. If the full scale 
output current of the 12-bit DAC were 10mA, the weight of 
the LSB would be 4.9|iA which would be too low to achieve 
high speed switching. Additionally, with all those switches 
in parallel, the output capacitance would become quite high. 
The only redeeming feature of a binarily weighted DAC is 
that there would be no wasted current and the net power 
dissipation for this type of digital to analog converter would 
be the lowest as compared to other design approaches. 

Another way to approach this design would be to have 
twelve equally weighted current switches. The twelve equally 



weighted current switches would then be binarily weighted 
by passing their currents through an R-2R ladder as shown 
in Figure 56. Twelve equally weighted current sources could 
then be precisely matched using a "servo mechanism" con- 
trol loop as shown in Figure 57. The servo loop is able to 
cause the value of the output current to be exactly (within 
circuit tolerances) the same as the reference current. A 
reference current is connected to the positive input of the op 
amp and the collector of transistor Qj. The same reference 
current then passes through Qj and emerges as emitter 
current by the addition of base current. The emitter current 
of Qj then becomes the collector current of Q 2 . The voltage 
current developed across the base to emitter junction of Q 2 
and the voltage drop across R! create an identical current 
through Q 3 . The collector current of Q 3 becomes the emitter 
current of Oj which in turn emerges from Q5 as the output 
current. Examination of the analysis shown in Figure 57 shows 
that if all the transistors and resistors are well-matched, the 
output current will be equal to the reference current. This is an 
ideal technique to be implemented in a monolithic process, as 
it is very practical to make transistors and resistors identical. A 
more detailed analysis of error sources will be shown later. A 
digital to analog converter designed in this manner would have 
the lowest glitch performance but at the expense of the highest 
power dissipation. "Glitch" refers to the uncertain DAC output 
that occurs when the digital input changes and the DAC 
switches do not change simultaneously. More will be given on 
the design of low glitch DACs toward the end of the section 
on high speed digital to analog converters. 

Practical digital to analog converters are a mixture of the two 
previously described examples as shown in Figure 60. Start- 
ing with the MSB (most significant bit), the currents are 
binarily weighted until the current becomes low enough to 




FIGURE 57. DAC Servo Loop. 



211 




V 1V 
l = C-^- =1pF— =1mA 
ns 



FIGURE 58. DAC Switching. 



effect switching speed. Even though the MSB currents are 
not the same value as the LSB currents, matching is main- 
tained as the current density is made to be the same. The 
current density is maintained by making the transistors that 
are to conduct larger currents physically larger, thereby 
causing the voltage drop associated with the transistor to be 
the same. This is similar to placing transistors in parallel. 

Figure 58 shows a diagram depicting the switching of one 
DAC current switch. This type of an emitter coupled pair is 
capable of switching very rapidly in response to a positive 
going input logic change as Q[ acts as an emitter follower 
which is capable of driving the capacitance attached to the 
common mode where the emitters of Qj and Q2 are joined. 
If the base of Q] is driven from and ECL input the speed at 
the emitter of Q, is determined by the rate of change of the 
ECL input of about 1 V/ns. To obtain low glitch performance 
it is necessary to have the DAC propagation delay to be 
equal for negative as well as for positive logic changes. 
Therefore, when the logic input makes negative going tran- 
sition the current supplied by current source Q 3 will have to 
provide enough current to drive the node capacitance to 
allow the voltage change at the emitters to track the negative 
going input signal. Some digital to analog converter designs 
will drive the current switch differentially, which means that 
either side of the switch is capable of actively driving the 
node capacitance instead of depending upon the current that 
is being switched. While this approach solves the problem of 
providing high current for the lower order bits, it does so at 
the expense of providing a differential driver. If done so 
externally, the chip would have to have an additional twelve 
inputs as well as require that the user supply differential 
inputs. Alternatively, a differential driver could be placed on 
the chip at the expense of loss in speed and extra circuit 



complexity. This particular approach is taken to emphasize 
simplicity. Returning to the design at hand: the amount of 
current necessary to follow a negative going logic change is 
given by the formula (see Figure 58): 

I = C(V/T) 

where C is the total node capacitance and (V/T) is the rate 
of change of the logic input. 

Substituting: 

I = lpF(lV/ns) = 1mA 

An extra amount of current is provided to assure equal 
propagation delays in both directions so that the minimum 
current that is set for the lower order bits is 1.25mA. The 
MSB current switch is scaled to be four times this value of 
5mA and the next bit, Bit 2, is scaled at twice the minimum, 
or 2.5mA. Bits 3 through 12 are then set at 1.25mA. Bits 1 
through 3 are connected together while Bits 4 through 12 are 
passed through the R-2R ladder to establish the proper 
binary weighting. In order to maintain high accuracy, Bits 1 
and 2 are also physically scaled. Physical scaling can be 
thought of as placing unit current switches in parallel, 
thereby allowing proper matching and compensation by the 
servo amp. Figure 59 shows how this is done. 

Typically the output resistance of the ladder is 250Q (see 
Figure 60), so the DAC output voltage swing will be 2.5V. 
For greatest flexibility there is a resistor connected to the 
positive reference that allows that DAC output to be able to 
swing +1.25V around ground. In order to accommodate the 
negative level of -1.25V, care must be taken so the output 
transistor is not saturated. Figure 61 shows a circuit diagram 
that includes the parasitic collector resistances which must 
be accounted for. This diagram also shows the translation 



FIGURE 59. Scaled Transistors. 



1.25mA 
Transistor 



6.8 



7.6 
-8.5 




-13.5V 



R . 135-10.7 =2 _ 24kn 



1.25mA 



FIGURE 61. DAC Bias Voltages. 




DAC Out 



5 ^ 



:25on 



125Q- 




Bit 2 



, 5mA 



125U 
WW 



125Q 125Q 

-vW MM 



Bit 3 



\ 2 - 



5mA 




Bit 4 



J, 



25mA 



Bit N 



1.25mA 



J_ 




-ov„, 



25mA 





► r 3 ; 













-15 V 



FIGURE 60. Practical DAC. 




zener so that the DAC switch can properly interface to the 
ECL level inputs. A 6.8V zener is a useful voltage transla- 
tion device as the impedance level is low, about 50Q, which 
is necessary for maintaining high speed. When the ECL 
level is at a low of -1.7V, the voltage at the base of Q x will 
be -8.5V. Since the voltage at the base of Q 2 is -8.1V, Ch 
will be off and Q 2 will be on. Even though Q! is slightly 
forward biased, the amount of conduction is tolerable for 12- 
bit applications. The voltage at the emitter is then -8.8V 
when Q 2 is on. The saturation resistance for the transistors 
used in this DAC design is lk£2 and since the current level 
is 1.25mA, the voltage at the actual collector is -10V. Under 
worst case conditions, the base voltage should not be al- 
lowed to become greater than -10V or the onset of saturation 
will begin. Therefore, under these conditions the emitter of 
Q 3 will be at -10.7V. It is always desirable for maximum 
accuracy (as will be shortly seen) to create as large an 
emitter degeneration voltage as possible. The largest voltage 
tolerable will be when the emitter voltage is -10.7V and the 
power supply voltage, which is nominally -15V, is at its 
lowest of -13.5 V. Under these conditions the emitter degen- 
eration voltage will be: 13.5 - 10.7 = 2.8V. The emitter 
degeneration resistance will then be (2.8V)/( 1.25mA) = 
2.24kft. 

Refer to Figure 62, which shows an analysis of the principal 
error-producing elements of a typical DAC switch and 
current source. There are three error sources that can be 
eliminated by adjustments after the DACs are assembled and 
two sources of error that must be eliminated by design. The 
three sources of error that can be adjusted to zero or 
"trimmed out" are the beta and V BC matching of the tran- 
sistors and the matching of the thin film resistors. While 
these error producing effects can be corrected at room 
temperature, they will change over temperature. As an 
example: The beta of a transistor will be assumed to be 150 
and to have a temperature coefficient of +7000ppm/°C An 
uncompensated transistor collector current will experience a 
beta error of (7000/C)/150 = 47ppm/°C. This means that at 
room temperature the ratio of the collector to emitter current 
will be 150/151 = 0.99348 and at 125°C the ratio will be 
0.99609. Due to the compensation action of the servo-loop, 
experience has shown that a further reduction by a factor of 
200 can be attained so that the net drift over temperature due 
to this effect is 0.24ppm/°C. If transistors Q 2 and Q 3 are 
carefully matched, their V BE s will track each other to l|iV/ 
°C and the effect upon the accuracy of the switch will be 
(lu.V/°C)/2.8V = 0.36ppm/°C. Lastly, resistor matching of 
0.5ppm/°C is achievable if the resistors are laid out properly. 
Adding these three effects yields a net current source drift 
over temperature of: 

Change over temperature = (2)Beta + V BE + Resistor 
= 0.47 + 0.36 + 0.5 = 1.33ppm/°C 

Assuming that these errors can be laser-trimmed to arbitrary 
accuracy at room temperature, any bit switch over a 100°C 
temperature change will experience a 133ppm change which 
implies that if these assumed tracking values were attained 




= 0.5ppm/°C + 0.36ppm/°C + 0.47ppm/°C 
= 1.33ppm/°C 



FIGURE 62. Trimmable DAC Errors. 

it would be difficult to produce with high yield a DAC that 
had ±1/2LSB linearity. The art of building high accuracy 
digital to analog converters is the ability of design, layout, 
processing, and manufacturing engineers to control the pre- 
viously described elements to sufficient accuracy. In fact it 
is possible to manufacture 12-bit DACs from -55°C to 
+125°C within ±1/2LSB accuracy and the above assumed 
parameters are achievable. 

There are two other sources of error that can only be 
eliminated by proper design: the output impedance and 
superposition error. Due to the cascoded nature of the DAC 
switch, the output resistance is given by (see Figure 63): 

Rout = (Beta)(V A /I) (V A = Early voltage) 
= (150)(200/10) 
= 3 Meg 

Since the ladder impedance is 250Q, the output resistance 
represents an error of 83.3ppm which is below the error 
budget of 122ppm needed for a 12-bit design. The output 
resistance causes a non-linear error since there is a differ- 
ence in this value when the switch is on compared to the off 
value. 

The last error source that needs to be considered is 
superposition error. Superposition error occurs when the 
individual bits do not add up to the proper sum defined by 
their values when they are individually turned on. 
Superposition error can have many causes, but one of the 
most prevalent causes for the type of DAC being discussed 
is the offset created by the resistance in the return line of the 




FIGURE 63. Error Due to R 0UT . 

R-2R ladder. Figure 64 illustrates how the DAC offset can 
be markedly different as a function of how many bit switches 
are turned on. If any individual bit is turned on, the offset 
will be equal to the bit current multiplied by the value of the 
resistance in the ladder return. As long as only one bit switch 
is turned on the offset voltage will be constant. However, 
when multiple bit switches are turned on this error will not 
be constant. Take the case when the DAC makes a 1LSB 
transition around the MSB. When the MSB is on, the offset 
voltage is the small value defined by only one switch being 
on. However, 1LSB below the MSB occurs when the lower 



eleven bits are turned on with the MSB off, and this offset 
voltage will now be eleven times greater compared to when 
only the MSB is turned on. This effect can be minimized by 
making the ladder return impedance as small as possible and 
by returning the opposite side of the bit switch back to the 
same point as the on side is to be returned to. This has the 
effect of keeping this offset voltage constant for any digital 
code combination. It is important to sense the voltage at the 
true reference point on the ladder to achieve maximum when 
the DAC is trimmed at the factory level. 

This digital to analog converter has the capability of settling 
to ±0.01% accuracy for a full scale change in about 26ns. 
The settling time is primarily determined by the ladder 
impedance and the total capacitance that is accumulated on 
the output node. The combined capacitance of the R-2R 
ladder, the offset resistor, the output transistors, and the load 
capacitance is about lOpF. The propagation delay from the 
digital input to the actual current switch is 3ns. The remain- 
ing part of the settling time is due to the voltage settling of 
the output time constant formed by the ladder impedance of 
250Q and the node capacitance of lOpF which forms a 2.5ns 
time constant. Settling to ±0.01% accuracy requires (2.5) 
ln( 1/0.01%) = 23ns, and when the digital propagation delay 
is added to the voltage settling, the total becomes 26ns. 
Achieving fast and accurate settling times requires paying 
attention to several other aspects of the design that will be 
described. Improperly designed reference and servo-amp 
circuitry can lead to a DAC that will not achieve the 
previously calculated 26ns. Figure 65 shows a path of how 
the digital input coupled onto the fence line which deter- 
mines the value of the bit currents. The servo operational 



Improper 
Connection i 



Proper / 
Connection 



2R 




l-l 1 + l 2 + l 3 + l 4 +... + l 12 
Resistance in Ground Line 



I2R 



R 








v MSB = R(l/2) + RI- 
Vu»-i-r(|-^)*R(1DI 



Offset for Single Current Source 



-Offset for Multiple 
Current Source 



FIGURE 64. Superposition Error. 



215 




-ov+ 



o.or 



iasO^Q, AH^ ^~° V ' 






/ L 




0.01" 


►— i [ 




>-R 2 







i |-"— Digital Delay 



O 
V- 



Settting Time = Digital Delay + Ladder Response 

= 3ns + R L C L '"(j^-) = 3ns + (250O)(10pF) In (+0.01%) 
= 26ns 



FIGURE 65. Settling Time. 



amplifier would have to have a bandwidth of 25MHz to 
50MHz to be able to respond and to settle to the capacitively 
injected transient onto its output. This is not a practical 
requirement since only the fastest op amp can settle in 24ns 
even if separately designed and not part of a DAC chip. A 
more practical solution would be to place a 0.0 lpF capacitor 
on this reference line to absorb the transient and then design 
a low frequency op amp that was stable. 

The switches that form the DAC are unipolar and in its 
natural form the DAC has an output that swings from ground 
to some negative voltage. For maximum flexibility it is 
desirable to have a bipolar DAC which requires a means of 
translating the output voltage in a positive direction. This is 
accomplished by connecting a 1.2kQ resistor back to the 
7.5 V reference voltage. Examination of Figure 65 reveals a 
buffer compound emitter follower that is used to isolate the 
low current offset resistor. This buffer isolates the reference 
offset current change from entering the low bandwidth 
reference and servo-amp circuitry. A O.OlftF capacitor is 
added to the isolation circuit to prevent transients from 
entering the low frequency servo-loop. 

Ordinarily a designer would not consider the use of an ECL 
DAC but there are several reasons that the DAC previously 
described will have superior performance compared to a 
TTL DAC. Briefly, ECL has a lower logic delay than TTL, 
is less noisy, and ECL data registers have lower data skew. 



Data skew occurs when all the digital inputs do not change 
at exactly the same time and is defined as the difference 
between T PD (+) and T PD (-). T PD (+) is the positive going 
propagation delay while T PD (-) is its negative counterpart. 
As an example of this phenomenon, consider the major carry 
change for a 12-bit DAC. For a 1LSB change around the 
MSB, the code would change from 01 1 1 1 1 1 1 1 1 1 1 to 1000 
0000 0000 under ideal conditions. With the presence of data 
skew all bits might not change at the same time and an 
intermediate code could exist. Consider what happens if the 
MSB changed more rapidly compared to the rest of the bits, 
so that the code transition pattern would be: 

0111 1111 1111 -» 1111 1111 1111 -» 1000 0000 0000 
code before intermediate code code after 

See Figure 66 which shows a timing diagram depicting data 
skew. Therefore, for a period of time equal to the data skew, 
the DAC output would start to head in the direction of an 
output that was considerably different than a 1LSB change 
from the previous code. This large transient-like waveform 
that is created by data skew is often referred to as a DAC 
output "glitch." A convenient way to specify the glitch is by 
measuring the area of the glitch in units of LSB-ns. This is 
a more effective method for specifying the glitch than if it 
were defined as a voltage amplitude, as one could not 
compare DACs with different full scale output levels. Addi- 



Data 
Skew 




0111 1111 1111 
Before 
Change 



1111 1111 1111 
During 
Glitch 



Data 
Skew 



1000 0000 0000 
After 
Change 



FIGURE 66. Skew. 



Data Skew 



V\AA- 



-OV D 



e (D 



e (t) - — — HT'Rc) = (V p T) • 2n f D e^'oi 
R C 



/ 



e (t) dt - • RC (1 - e-< T ' R c>) 
RC 



■VpT 



FIGURE 67. Glitch Response. 



DAC 
Output 



Glitch 

wt 



Track/Hold 
Command 



Amu. 



^-Hold 

Track 



Register 



Track 
Hold 



-O 



Deglitched Output at Clock 
Track/Hold Output 



T/H 



oanuwiuin ampuiier, mc pea*, ampuiuue ui uic gincn wouiu 
change but the area under the curve would not. Assume that 
the glitch response of the DAC is a pulse with a width equal 
to the data skew and with an amplitude of 1/2 full scale. 
Figure 67 shows that the area under the time response of the 
glitch is constant. Examination of the time response of the 
glitch indicates that the peak glitch amplitude is a function 
of the bandwidth of the amplifier. For that reason, a more 
reliable way to specify the glitch performance of the DAC is 
by the ET product, or in LSB-ns as ET is independent of the 
bandwidth. Further note that the average value of eo(t) is equal 
to ET and is independent of the bandwidth of the amplifier. 
What this means is that, as the bandwidth is reduced, the 
peak amplitude will diminish but the effect of the glitch will 
last longer. 

An ECL DAC will generate a lower glitch than a TTL DAC 
but there are systems where the glitch has to be further 
reduced. For these applications the DAC is followed by a 
track and hold as shown in Figure 68. The track and hold is 
placed in the hold mode prior to the register being clocked. 
After the register is clocked and the digital to analog con- 
verter is allowed to settle, the track and hold is then placed 
back into the track mode. In many systems the non-uniform 
nature of the glitch response creates distortion and harmon- 
ics and even though the track and hold may actually have a 
greater glitch than the DAC, the glitch is uniform for all code 
combinations and will manifest itself at the system level as 
an offset or gain error but not as a code dependent non- 
linearity. 




FIGURE 68. Deglitched DAC. 



FIGURE 69. Arbitrary Waveform Generator. 

Figure 69 shows a system with a high speed digital to analog 
converter that can be used to generate a precise arbitrary 
waveform. While there are many ways to accomplish this 
with lower frequency circuitry, the use of a high speed DAC 
is an attractive alternative. A high frequency DAC is capable 
of being updated at a 50MHz rate, which will substantially 
ease the subsequent analog filtering requirements. Since the 
waveform is effectively sampled at a 50MHz rate it would 
be possible to create a waveform with frequency compo- 
nents up to the Nyquist rate of 25MHz. Generating an 
arbitrary waveform is the inverse of digitizing a waveform 
with an analog to digital converter and the same sampling 
considerations apply. Figure 70 shows an arbitrary analog 
waveform that is to be synthesized. If the waveform were 
sampled at periodic intervals, the synthesized waveform 
would be created. The synthesis procedure consists of math- 
ematically computing the closest 12-bit approximation to 
each sample point which would be used to generate the 







Word M - 1 
i«--WordM 
Word M + 1 


Word 4 / 






Word 3 j [ 






Word 2 — /] ! 






Word1-V| ] | 
I ! ' ! 






1 ! • 
ill! 

1234 

Clock 


M-1 M M + 1 





FIGURE 70. Arbitrary Waveform. 

encoding table for the ROM. Refer to Figure 69 which 
shows a simplified block diagram of a system that will 
generate a synthesized waveform. The sample points would 
correspond to the ROM address while the ROM output 
would be the associated code at each one of these addresses. 

DIFFERENT HIGH SPEED ADC ARCHITECTURES 

This section will compare the performance features, and 
trade-offs, of three commonly found architectures of high 
speed analog to digital converters to gain an understanding 
of how resolution, speed, and complexity interact in the 
design of an analog to digital converter. These three archi- 
tectures form the basis of most high speed ADCs that are on 
the market, although there are many variations of these basic 
circuit arrangements due to the nature of particular technolo- 
gies. It is useful, though, to gain an understanding of the 
architectures in their most elementary form before an appre- 
ciation of the variations can be gained. Each architecture has 



distinct characteristics that need to be properly understood to 
maximize the benefits of the chosen analog to digital con- 
verter with the application. 

The three types of designs that will be compared are flash, 
successive approximation, and sub-ranging. Each method of 
conversion has strengths and weaknesses which will be 
clearly contrasted. This section will compare the relative 
merits of each converter with respect to accuracy, dynamic 
characteristics, aperture effects, simplicity, and cost. A de- 
scription of each analog to digital converter will first be 
given which will then be followed by the performance 
features of each architecture. 

FLASH ADC 

The fastest of all types of high speed analog to digital 
converters, and perhaps the easiest to understand, is the flash 
or parallel type of converter. The flash converter is consid- 
ered to be the fastest because the conversion takes place in 
a single cycle, hence the name "flash." The resolution of 
flash converters is typically 8 bits, although expensive or 
experimental designs have been reported with up to 10 bits 
of resolution. Flash converters are very appealing to mono- 
lithic designers due to the highly repetitive nature of the 
design. Refer to Figure 71 which shows a block diagram of 
a flash converter. Speeds of up to 500MHz have been 
achieved and conversion times of up to 200MHz are readily 
available on the commercial market. Bipolar technology is 
used for the fastest designs with CMOS achieving conver- 
sion rates of up to 30MHz. The resolution of a flash con- 
verter tends to be limited to 8 bits due to the fact that the 
amount of circuitry doubles every time the resolution is 
increased by 1 bit. The input comparators are arranged in a 
"thermometer" code fashion with each comparator's refer- 
ence biased 1LSB higher that of the adjacent comparator. 
The reference for each one of the comparators is derived 



Analog Input 



-Ref 




R 3 9 R (2M-2) R (2"-1) R (2"j 

~vW Mrf — Mr T — \Mr~° +Ref 



Comparator 



Clock O- 




Linear to Binary Encoder 



Output Stages (Output Register) 



A 



B N-1 B N 



FIGURE 7 1 . Block Diagram of a Flash Encoder. 



from a series connection of a string of resistors that is placed 
between the negative and positive reference. This resistor 
string is monotonic by design but it is possible for the entire 
flash converter not to be monotonic due to the comparator 
offset. This condition could possibly occur if the reference 
voltage is set too low thereby enabling the offset of the 
comparator to dominate the effective reference level which 
is the sum of each. Figure 72 illustrates this point. Suppliers 
of flash converters are able to produce monotonic results and 
still maintain LSB weight of 5mV, although LSB weights of 
lOmV are required for +1/2LSB linearity. The output of the 
comparators must be converted to a more economical digital 
code to be convenient to use. The thermometer code is 
typically converted to a conventional binary output. To 
achieve high sampling rates, digital pipelining is often em- 
ployed in the design of the flash converter. This has the 
benefit of enabling a new sample to take place before the 
previous binary code has been formed. 

The design of a comparator that is often employed in a flash 
converter is somewhat different compared to the design of a 
stand-alone comparator. The comparator input stage is con- 
figured to have a low gain state while in the tracking mode, 
and a high gain state while it is making the transition to the 
held state, the held state being the result of the comparison 
between the two inputs at the moment of sampling. Sam- 
pling takes place when a strobe pulse initiates positive 
feedback thereby causing regenerative action to take place 
which then sets the output of the comparator based upon the 
condition of the input. This method of design is necessary to 
achieve the simplicity required for a high resolution flash 
converter. Figure 22 shows a circuit diagram of a typical 
comparator stage of a flash ADC. 

As previously mentioned, CMOS technology is employed in 
the design of low power flash converters with conversion 
rates of up to 20MHz. One of the drawbacks of CMOS 
comparators is that their offsets are much higher compared 




to bipolar comparators. Low offset comparators can be 
achieved in CMOS by use of the "auto-zero" technique. 
Figure 73 shows a diagram of an auto-zero comparator. 
Designing an auto-zero comparator is practical in CMOS 
because of the high impedance nature of CMOS. The auto- 
zero comparator operates by going into the auto-zero mode 
for part of the conversion time and staying in the measure 
mode during the remaining time. While in the auto-zero 
mode the input coupling capacitor charges up to the com- 
parator offset so that when the comparator is placed back in 
the measure mode, the voltage on the capacitor is in such a 
direction to cancel the offset of the uncompensated com- 
parator. 

Dynamic performance is the one area that separates the 
performance of one flash converter from that of another. 
Dynamic performance is a measure of how a flash converter 
is able to accurately digitize a high frequency signal. This 
requires that the user understand how aperture jitter, aper- 
ture delay distortion and input bandwidth affect overall 
system performance. Input bandwidth is easily understood 
as this specification is similar to that of any band-limited 
device. The input bandwidth of a flash converter consists of 
both a small and large signal component that must be 
separately specified. Sometimes the large signal bandwidth 
is not directly specified but can be determined from the input 
slew rate. The input capacitance of flash converters can be 
high; therefore it is necessary to drive the encoder from a 
low impedance source to achieve high bandwidth. 

Another phenomenon that limits the high frequency perfor- 
mance of a flash converter is aperture time. Aperture time is 
defined as the effective point where the comparator makes 
its decision. It should be noted that the aperture time is 
actually the difference between the delay in the path that is 
processing the compared signal and the delay in the path that 
processes the strobe. This can become a serious source of 
distortion if the aperture delay of each comparator within the 




FIGURE 73. Auto Zero Comparator. 



FIGURE 72. Comparator Offset. 



219 



flash converter is different. As an example of this effect, 
consider how closely the aperture delay of an 8-bit, 200MHz 
flash converter needs to be matched to digitize a signal at the 
Nyquist rate while making only a 1LSB error. Aperture error 
is given by: 

T A = E„/(D Fs /D T ) 

Where: 

T A = aperture time 

E„ = allowable noise = 1LSB 

Fs = signal frequency 

D Fs /D T = max signal rate of change = (2 N )(LSB)(7)(Fs) 
Substituting: 

T A = LSB/(2 N )(LSB)(7t)(Fs) = 1/(256)(ji)(100E6) = 12.5ps 

If the effective analog bandwidth of each comparator were 
1GHz, the propagation delay of each comparator stage 
would be in the lOOps to 200ps range. It would then be 
necessary to match the delay of each comparator to 12.5ps 
to preserve the accuracy. Since flash converters can easily be 
250mils in length and the signal could take as long as 400ps 
to propagate the length of the chip. The physical layout of 
the chip is extremely important to achieve acceptable high 
speed performance. 

The high frequency performance of most analog to digital 
converters can be improved by conditioning the input signal 
by a sample and hold. This happens as the aperture distortion 
occurs due to the time delay of the individual comparators 
within the flash encoder not being matched. Since the 
sample and hold utilizes a single switch, the aperture perfor- 
mance of the combined system will be improved. One of the 
methods that can be used to determine the existence of 
aperture induced distortion is to measure the spectral re- 
sponse of the ADC by performing an FFT. This should first be 
performed at a low frequency to eliminate static accuracy as 
the source of the distortion. Aperture induced distortion will 
then be noted as the component of the distortion that increases 
with frequency. Even when a sample and hold is not required, 
interfacing an analog signal to a flash encoder deserves serious 
consideration. Both the input capacitance and resistance vary 
with signal level so it is important to drive these types of high 
speed converters with a low impedance source that can be 
supplied either from an op amp or from a buffer. This solution 
is not without its difficulties as high speed op amps are prone 
to oscillating when required to drive large capacitive loads 
characteristic of flash encoders. Usually, high speed op amps 
and buffers are capable of driving low resistive loads so it is 
possible to decouple the capacitive load from the driving 
source by placing a small resistor between the two. The 
resistor has the effect of making the impedance seen by the 
buffer look resistive thereby preventing an oscillatory condi- 
tion. Setting the value of the resistor between 10Q to 50Q has 
minimal effect on the system bandwidth. Reference to the 
beginning of this study will show numerous buffers and 
amplifiers that could be suitable for interfacing to a flash 
encoder. Refer to Figure 74 which shows how the coupling 
resistor helps stabilize the driving source. 




FIGURE 74. Buffer Driving Flash Encoder. 

It is straightforward to increase the resolution of a flash 
encoder by stacking two together as shown in Figure 75. It 
should be noted that two encoders stacked together in this 
manner will have poor aperture performance as matching the 
aperture delays of two separate encoders is difficult. This 
can be connected by driving the stacked flash encoders by a 
sample and hold. 




FIGURE 75. Stacked Flash Encoder. 

As previously mentioned, the resolution of flash converters 
is generally not greater than 8 bits. If the resolution of the 
converter were to increase by 1 bit, the amount of additional 
circuitry would have to double. Therefore, a 10-bit converter 
operating at the same speed as an 8-bit one would be four 
times as large and dissipate four times as much power. A 
conflict now develops when the designer attempts to use 
smaller geometry devices to reduce the size of the chip. With 
the use of smaller devices comes less accuracy which then 
compromises the possibility of achieving a 10-bit flash 
converter design. Similarly, the speed tends to be reduced to 
avoid excessive power dissipation on the chip. 



the design of analog to digital converters is successive 
approximation. Successive approximation has achieved this 
high degree of popularity because this type of design has the 
highest degree of performance for the cost. Figure 76 shows 
a block diagram of a successive approximation ADC. As can 
be seen from the block diagram, the circuit design is straight- 
forward, employing only a single comparator along with a 
digital to analog converter and the successive approximation 
logic. The previously mentioned comparators and digital to 
analog converter would serve as suitable subassemblies for 
a successive approximation ADC. Performance varies widely 
for designs employing this type of architecture, ranging 
from 8 to 16 bits of resolution with conversion rates from 
400ns to 25ixs. 



Convert Command 

o 



Clock 






Shift Register 







Latches 



Digital Output 
O 



Comparator 



Digital 
Analog 
Converter 




FIGURE 76. Block Diagram of Successive Approximation 
Analog-to-Digital Converter. 

Hybrid, discrete, and monolithic technologies are all used in 
the manufacture of this type of converter, with hybrid 
designs dominating the high performance sectors. Recently 
monolithic designs have been introduced that were formerly 
the exclusive province of converters designed with hybrid 
technology. Performance levels with 12 bits of resolution at 
conversion times of 3\is can now be achieved in monolithic 
form with speeds down to Ilis on the "drawing board." 
These single chip 12-bit ADCs employ bipolar, CMOS, and 
BiMOS for their design. Through BiMOS it is possible to 
use the most desirable features of CMOS and bipolar tech- 
nologies. BiMOS processing offers both technologies on the 
same process. CMOS is optimum for achieving high speed 
logic with very little power dissipation, and bipolar technol- 
ogy is better suited for low noise and high speed which is 
required by the analog section of the ADC. 



lUi ClUICi lliUllUIIUllO wilvwiiv^lb Ul 1U1 juppijiiig U1G lUglC 

function in hybrid designs. This is a very important develop- 
ment as CMOS offers lower power dissipation and current 
drain than bipolar logic. Both of these features are important 
to a system user as lower power dissipation leads to a lower 
temperature rise, greater reliability, and fewer problems with 
warm-up and temperature drift. Reduced current drain will 
enhance system accuracy as noise due to common analog 
and digital current paths will be reduced. At the present time 
successive approximation designs are dominated by the 
conventional R-2R ladder approach used by the digital to 
analog converter that lies within the ADC. Just over the 
horizon, several manufacturers have designs based upon 
charge distribution techniques employing CMOS. These 
newer CMOS designs also hold the potential of error correc- 
tion and self-calibration that will enable converters to achieve 
greater stability with time than can be achieved with bipolar 
converters. This arises from the fact that higher circuit 
density can be achieved with CMOS which is required to 
implement the error correction function. 

The successive approximation process begins with a start 
conversion pulse, setting the most significant bit to the "on" 
state with the remaining least significant bits in the "off 
state. The output of the digital to analog converter is sent to 
one of the inputs of the comparator. The other input to the 
comparator is the analog signal that is to be digitized. After 
allowing an adequate amount of time for the digital to analog 
converter to settle, the output of the comparator is read into 
a latch where the decision is made whether to keep the bit on 
or not. If the input signal exceeds the weight of the MSB, the 
decision is made to keep the bit on. During the next trial 
period, Bit 2 is turned on and added to the result of the initial 
MSB comparison. In the event that the signal was greater 
than the MSB but not as great as the sum of the MSB and 
Bit 2, the MSB would be left on with Bit 2 being left off. 
This process of adding one more bit and testing the state of 
the comparator continues until all the bits of the digital to 
analog converter have been exercised. Figure 77 illustrates 
this process. Figure 78 shows a timing diagram of the 
successive approximation conversion cycle. One manufac- 
turer adds digital correction to the conventional successive 
approximation algorithm. The first eight bits are converted 
only to 8-bit accuracy when the converter goes into a 
tracking mode to correct the conversion to 12-bit accuracy. 
This correction capability allows the first eight bits to 
operate at a higher sampling rate compared to conventional 
successive approximation. 

Successive approximation has achieved wide popularity due 
to the simplicity of the design. The linearity of the ADC only 
depends on linearity of the digital to analog converter which 
is typically not true of the other ADC architectures being 
compared. The offset of the comparator creates an overall 
offset but not a linearity error as would be created in a flash 
converter. The state of the art in producing accurate digital 



221 



.2.120V 




OAC Full Scale = 4.096V 







COMPARATOR 


DIGITAL 


TRIAL 


DAC 


INPUT 


OUTPUT 


1 


2.048 


0.072 


1 


2 


2.048+ 1.024 


-0.952 





3 


2.048 + 0.512 


-0.440 





4 


2.048 + 0.256 


-0.184 





5 


2.048 + 0.128 


-0.056 





6 


2.048 + 0.064 


+0.008 


1 


7 


2.112+ 0.032 


-0.024 





8 


2.112+0.016 


-0.008 





9 


2.112+ 0.008 


+0.000 


1 


10 


2.120 + 0.004 


-0.004 





11 


2.120 + 0.002 


-0.002 





12 


2.120 + 0.001 


-0.001 






Analog In V„ = 2.120V 
Digital Out 1000 0100 1000 



FIGURE 77. Successive Approximation Process. 



to analog converters is highly developed, which directly 
benefits successive approximation converters. ADCs em- 
ploying these DACs will have correspondingly wide tem- 
perature ranges. Typically, successive approximation ADCs 
will operate over a wider temperature range, compared to 
other techniques, and designs are even available that operate 
at 200°C. Sub-ranging analog to digital converters have 
additional sources of error that distort the linearity, as will be 
explained later. Since there is only a single comparator, 
more power can be applied to the DAC and comparator to 
reduce the overall conversion time. Additionally, a succes- 
sive approximation converter will naturally produce a serial 
form of the converted output. The serial output feature is 
very useful for economical digital transmission. Also, it 
lends itself for optical isolation techniques which helps 
reduce the interaction between the analog and digital sec- 
tions of the processing system. With this design, only the 
DAC has to settle to the final accuracy. This is not true of the 
sub-ranging arrangement as will be explained later. Assum- 
ing that the conversion rate could be achieved, successive 
approximation would be the architecture of choice as a 
higher level or performance can be obtained at a given 
selling price for a particular conversion rate. Another attrac- 
tive feature of successive approximation is that speed can be 
traded off against accuracy. Accuracy will degrade gradu- 
ally due to the DAC not settling and the additional overdrive 



Start 




n 












Bit1 
Bit 2 


n 




n 


Bit 3 


n 






n 


Bit 4 


n 




n 


Bit 5 




n 




n 


Bit 6 




i 


i 


i 


Bit 7 




n 




n 


Bit 8 




n 




n 


Bit 9 






i 


i i 


Bit 10 




n 




n 


Bit 11 




n 




_TL 


Bit 12 










DAC 










r 

Comparator 


n n 


n n n 













FIGURE 78. Timing Diagram of a Successive Approximation Converter. 




FIGURE 79. Speed vs Accuracy. 



needed to switch the comparator more rapidly (see Figure 
79). This tradeoff happens gradually, and very often a 
designer can increase the throughput rate of the system with 
only a moderate decrease in accuracy. This tradeoff is not 
possible with the other two architectures being compared, 
because once the stated conversion rate is exceeded, the 
accuracy degrades rapidly. Figure 80 shows this character- 
istic, which is common to successive approximation ADCs. 

The aperture time of a successive approximation ADC is the 
conversion time. This occurs because it is necessary to hold 
the signal constant during the time when the conversion is 
taking place. If this does not occur, serious linearity errors 
will develop. This results from the fact that the conversion 
is not essentially instantaneous as it is with the other con- 




* 

0.8 1.0 1.2 1.4 1.6 1.8 
Conversion Time (us) 



verter types that are being compared. It then becomes 
necessary to condition the signal that is to be digitized by a 
sample and hold and not by the ADC. This is true whether 
the input signal is making rapid changes or not. The sample 
and hold must hold the signal constant during the ADC 
conversion time. Therefore, the only effect that is experi- 
enced by the ADC is varying signal levels on the comparator 
input which generally has a rapid recovery time. 

A potential source of error that needs to be considered is 
when the comparator has been converting at one extreme of 
the input range and the signal changes to the opposite 
extreme. If the comparator is not properly designed, the 
analog to digital converter will experience a thermally in- 
duced offset that will cause multiple conversions not to be 
the same until thermal equilibrium is established. The sys- 
tem designer must also allow for sample to hold settling to 
take place as this could become a source of error — the input 
signal will not be the same during the conversion cycle time. 
Before the section on successive approximation converters 
is completed, an application problem needs to be mentioned. 
As the converter is going through the conversion cycle it is 
possible to inject a transient waveform into the source which 
is generated by the DAC. As the DAC value is being 
programmed by the logic the "summing junction" at the 
input to the comparator is not balanced and a signal will be 
injected into the sources. It is therefore important to drive 
high speed successive approximation ADCs with sources 
that have adequate settling performance or the rated linearity 
performance will not be achieved. The use of a common 
mode comparator arrangement can help to alleviate this 
problem by isolating the DAC from the input by the 
comparator's common mode nature. See Figure 81. 

SUB-RANGING ADC 

The final architecture to be studied uses the sub-ranging or 
two-step technique. Both names are descriptive of these 
types of analog to digital converters. Sub-ranging converters 



input 




FIGURE 80. Speed vs Accuracy. 



FIGURE 81. SAR ADC Input. 



223 



Sample 
and 
Hold 



MSB 
Flash 
Encoder 
M Bits 



DAC 




Amp 



LSB 




Digital 


Flash 




Error 


Encoder 




Corrector 


LBits 






(Adder) 



Digital 
Output 



FIGURE 82. Block Diagram of Sub-Ranging ADC. 



are considered by designers when high resolution is required 
for conversion rates that are faster than can be achieved with 
successive approximation. As an example, a two-step design 
becomes the approach of choice when the system engineer 
requires 12 bits of resolution at conversion rates lower than 
1 u.s. This transition point between successive approximation 
and sub-ranging changes somewhat when lower resolution 
is required. Ten-bit performance can be achieved at conver- 
sion rates lower than 0.5lis using successive approximation. 

Sub-ranging combines the elements of the two previously 
mentioned design techniques. All technologies are employed 
to produce sub-ranging designs varying from monolithic to 
modular. Flash converters only require one conversion cycle 
although 2 N comparators are necessary. Successive approxi- 
mation uses only one comparator but N conversion cycles 
are needed. Sub-ranging is a mixture of the two, as an N-bit 
converter would use two cycles of an N/2-bit flash con- 
verter. As an example, a 10-bit flash encoder would use 
1023 comparators while a successive approximation type 
would use one comparator and a sub-ranging design would 
use 62 comparators. It should be noted that the sub-ranging 
ADC to be discussed uses only two ranges or conversion 
cycles. In general, more steps can be used and often find 
their way into higher resolution converters. The principle of 
operation is similar and for purposes of simplicity only the 
two-step version will be explained. 

Refer to Figure 82 which shows a block diagram of a sub- 
ranging converter. The analog signal is initially sent to a 
sample and hold to reduce aperture effects and to optimize 



AC performance. The output of the sample and hold then 
goes to an M-bit flash encoder and to a subtracter. After the 
sample and hold has acquired the signal and the sample to 
hold transient has decayed, the first encoder is strobed. The 
first encoder output determines the initial coarse approxima- 
tion to the input signal. The digital output from the first 
encoder is sent to a digital to analog converter where it is 
converted back to analog form. This signal is then subtracted 
from the output of the sample and hold. The subtracted 
signal is then amplified before being applied to the second 
encoder which has L bits of resolution. The second encoder 
is also strobed with each encoder's output being sent to a 
digital adder where the final output word is created. 

For a sub-ranging design to operate properly, it is necessary 
for (M + L) > N. These extra bits are used to encode 
internally developed errors which are capable of being 
corrected by a simple algorithm. Figure 83 helps to explain 
the operation of digital correction within a sub-ranging 
converter. The simplified analysis shown, in Figure 83, 
shows that the output of the ADC, with error correction, 
does not contain the error of the MSB encoder. This means 
that 12-bit accuracy can be achieved even though the MSB 
converter only has 8-bit accuracy. The output only contains 
the error of the LSB encoder which is reduced by the gain 
of the amplifier that precedes it. For simplicity the DAC 
error has been left off of the diagram shown in Figure 83 but 
has been shown in Figure 82. The DAC error has been 
omitted from the analysis because it has been assumed that 
the DAC is perfectly accurate. High speed DACs can achieve 




Output 



System Input e IN 

MSB Flash Out e, N + Ae m , Ae m - MSB Flash Error 

Input to LSB Flash e IN - (e, N + Ae m ) - -Ae m 

Output from LSB Flash -Ae m + Ae d , Ae d = LSB Flash Error 

Digital Output e IN + Ae m + (-Ae m + Ae„) = e IN - Ae d 



FIGURE 83. Error Correction. 



Device Under 
Test 




Test Signal 
Generator 



Digitally 
Programmable 
Delay 



DVM 



Computer 



FIGURE 84. Waveform Digitizer. 

14-bit accuracy, so this is a reasonable assumption. Another 
attractive feature of digital correction is that sample to hold 
settling errors can be corrected and will not lead to linearity 
errors as they do with successive approximation converters. 
The sample to hold settling error would be included as part 
of the MSB error. The M and L bit lines from each of the 
lower resolution encoders are then combined in the digital 
adder to form the final output word. To maintain high 
throughput rate the combining takes place during the next 
conversion cycle while the next data sample is being taken. 

The adder, registers, and timing are grouped together and 
play the same role as does the successive approximation 
register of the single comparator design. Sub-ranging con- 
verters have achieved 12 bits of resolution with sampling 
rates to 20MHz. 

TEST TECHNIQUES 

There are numerous methods for evaluating the performance 
of the many components that comprise a data acquisition 
and conversion system. A few useful techniques will be 




may be other techniques that are not mentioned, although the 
technical literature is replete with these other techniques. 

SETTLING TIME 

The most powerful technique than can be employed to 
evaluate the settling time of a DAC or an amplifier is to 
digitize the waveform under test. Once the waveform is 
digitized, the waveform can be sent to a computer where 
software routines can be used to determine the performance 
of the device under test. Digitizing the waveform is superior 
to hardware-oriented instrumentation because of the versa- 
tility associated with a computer. Once the waveform has 
been digitized, any property of the waveform can be ana- 
lyzed with the same hardware. Figure 84 is a block diagram 
of the digitizer. The waveform under test is fed to the 
inverting comparator input. The comparator's digital output 
is integrated by the op amp and fed back to the input. Figure 
85 is an illustration of the sampling or digitization process. 
The sampled waveform shown in Figure 85 is a crude 
representation of the original signal and was done this way 
for purposes of the illustration. In actual practice, sampling 
is performed in fine increments to achieve high accuracy. 
Sampling of the waveform under test is accomplished by 
repeatedly strobing the comparator at a selected time point, 
until the integrator feedback forces the comparator reference 
input to equal the sampled value of the input signal. Once the 
loop settles, this value is read by the DVM and sent to the 
computer. The sample is then incremented by the computer 
through the programmable delay. 

APERTURE JITTER 

Determining the aperture jitter of an ADC or sample and 
hold can be accomplished by the block diagram shown in 
Figure 86. This system avoids introducing any additional 
error due to instrumentation induced jitter as the added delay 
is a passive delay line. When the sampling signal is the 
signal being sampled there is no possibility of instrument 




Delay Line 

T 



Device 
Under 
Test 



Strobe 



Oscilloscope 



Aperture Jitter . 



dV 
dT 



FIGURE 85. Waveform Sampling Process. 



FIGURE 86. Aperture Jitter Measurement. 



225 



induced noise affecting the measurement. Once the delay is 
adjusted so the maximum rate of change section of the signal 
is being sampled, the aperture jitter T A is determined by the 
relationship: 

T A = EJ(dV/dt) 

Where: 

E,, = measured noise 

(dV/dT) = input rate of change 

BEAT FREQUENCY TESTING 

Beat frequency tests are qualitative tests that provide a 
quick, simple visual demonstration of dynamic ADC perfor- 
mance. Figure 87 shows a block that is used to perform a 
beat frequency evaluation. An input frequency is selected 
that provides the worst case change. This usually occurs at 
the Nyquist rate. The name "beat frequency" describes the 
nature of the test. The sample frequency is chosen to be a 
multiple of the input frequency plus a small incremental 
frequency (see Figure 88). By choosing a low beat fre- 
quency, the dynamic performance of the DAC does not 
affect the accuracy of the measurement. With the block 
diagram shown, the output of the ADC is resampled at 1/2 
the data rate to enable evaluation at the Nyquist rate. The 
beat frequency is set so that many samples are taken at each 
code. The beat frequency test should not be used as a 
substitute for more accurate methods for determining high 
frequency performance such as FFT measurements or histo- 
gram testing, but it provides a very effective method for 
optimizing the dynamic performance during the develop- 
ment stage of a project. The design engineer will get instant 
visual feedback, via the oscilloscope, to help pinpoint a 
circuit defect. This type of cause and effect relationship is 
not as easy to establish using more complex computer- 
oriented tests. Burr-Brown, of Tucson, Arizona, offers Ap- 
plication Note AN- 133, which describes many other dy- 
namic tests for evaluating ADC performance. 

SERVO LOOP TEST 

Figure 89 shows the block diagram of a system that can be 
used to evaluate the DC integral and differential linearity 
along with the gain and offset of an analog to digital 
converter. The desired code that is to be measured is loaded 
into the digital comparator from the computer. Based upon 
the results of the comparison between the output of the ADC 
and the desired code, the comparator will command the 
integrator to slew until a balance is reached. Loop balance 




FIGURE 87. Block Diagram of Beat Frequency Testor. 




Af 



t t t t t t t t t t 

Resampling Signal (f s + Af) 



FIGURE 88. Beat Frequency Waveforms. 



Analog 
In 



ADC 
Under 
Test 



Digital 
Comparator 



c, 




A, 



Computer 



DVM 



FIGURE 89. Block Diagram of Servo Loop Test. 



The information providedtierein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



I 




BURR - BROWN 




APPLICA TION BULLETIN 

PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



227 



HEAT SINKING — TO-3 THERMAL MODEL 

Hubert Biagi (602) 746-7422 



A critical issue with all semiconductor devices is junction temperature (T,). T, must be kept below its maximum rated value, 
typically 150°C. The lower the junction temperature the better. 

The thermal circuit shown below allows temperature to be estimated with simple calculations. The temperature rise across 
each interface is equal to the total power dissipated in the device times the thermal resistance (PD • 0). An estimate of the junction 
temperature can be calculated using the following formula: 



T = T 


+ PD 




Where, 


9 IA " 9 JC 


+ CH 


+ e HA 



T A (°C) = Temperature of Ambient Air 
Tj (°C) = Temperature of the Semiconductor Junction 
PD (Watts) = Power Dissipated in Semiconductor 
9 JC (°C/Watt) = Thermal Resistance (Junction to Case) 
9 CH (°C/Watt) = Thermal Resistance (Case to Heat Sink) 
8 HA (°C/Watt) = Thermal Resistance (Heat Sink to Air) 
9., (°C/Watt) = Thermal Resistance (Junction to Air) 



The following example shows typical values for a TO-3 package mounted in two different ways — one for high power 
applications, the other for low power applications. The value for JC of 0.8°C/W is for the OPA512 operating under 
AC signal conditions. For DC signal conditions, 9 JC is about 1.4°C/W. 



Power Dissipated 
Junction 



PD 




IajwiaaaJ 



Ambient Air 



UNITS 


HIGH POWER 
APPLICATION 


LOW POWER 
APPLICATION 


Watts 


100W 


10W 


10W 


1W 


°C 


145°C 


37°C* 


158°C* 


39°C 


°C/Watt 


0.8 


0.8 


0.8 


0.8 


°C 


65°C 


29°C 


150°C 


38°C 


°C/Watt 


0.1 


0.1 


0.5 


0.5 


°C 


55°C 


28°C 


145°C 


37°C 


°C/Watt 


0.3 


0.3 


12 


12 


°C 


25°C 


25°C 


25°C 


25°C 



S77V 



* Note, the difference in junction temperature that thermal resistance 
can make even when operating at the same power level. 



CO 



Calculations begin at the bottom of the chart and assume 25°C ambient temperature in these examples. Each component of 
thermal resistance produces a temperature rise equal to the product of power dissipated and thermal resistance. The 
temperature of the junction is equal to the product of power dissipated and the total thermal resistance (PD • JA ). 

Thermal resistances can vary significantly with particular models and mounting. While values can be obtained from 
specifications, calculated temperatures should be confirmed by measurements made at the bottom of the case. 




The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



®1992 Burr-Brown Corporation 



AB-038 



Printed in U.S.A. January, 1992 



APPLICATION BULLETIN 229 



IMMI 



Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



MOUNTING CONSIDERATION FOR TO-3 PACKAGES 

By Hubert Biagi (602) 746-7422 



Proper mounting of TO-3 packages is required to assure rated 
performance and reliability. Although the procedures are 
simple, ignoring them can result in poor performance and 
catastrophic failure of the device. 

PACKAGE HANDLING 

The TO-3 package is a rugged hermetic package, but it can be 
damaged with improper handling. Excessive bending or twist- 
ing of the package pins can crack the glass seal around the pin 
and result in loss of hermeticity. If pin straightening is 
required, clamp the pin against the package base using needle- 
nose pliers. This will strain-relieve the pin during the straight- 
ening operation. 

Another potential problem is cracking the internal circuit 
substrate from bending of the package base. This can be 
caused by mounting the package onto a non-flat surface, 
improper use of a compressible thermal pad, or over-tighten- 
ing the mounting fasteners. 

TO-3 SOCKET 

The Burr-Brown 0804MC TO-3 socket is designed to meet 
the requirements of high current, high power products such as 
the OPA512, OPA541, and OPA2541. The socket has a 
rugged contact design which assures positive and reliable 



contact even when using thermal grease and pre-tinned pins. 
The closed-ended contacts will accept the full pin length of the 
TO-3 and guard against solder and flux contamination. The 
socket body has a center hole which allows for direct measure- 
ment of TO-3 case temperature. 

FASTENERS 

The fastener hardware used to mount the TO-3 package is very 
important. Table I describes the proper hardware combina- 
tion. Sources for fastener hardware are listed at the end of this 
bulletin. The preferred fastener material is stainless steel. 
Plated steel is a good alternative. Brass or plastic fasteners are 
not recommended. 

The mounting holes of the TO-3 package are designed to 
accept 6-32 machine screws; no other size should be used (see 
exploded views in Figure 1 A and IB). The pan-head is the best 
head style. It has a low profile and large bearing face to 
properly cover the mounting hole, but its not so large as to ride 
up onto the lip of the welded cover. 

In order to maintain proper mounting pressure, the Belleville 
spring washer (also known as a conical compression washer), 
is recommended. Split ring and star lock washers are not 
recommended. They typically bottom out at less than 50 
pounds, whereas 150-300 pounds of pressure is needed to 



CO 

T- 

im 

CD 

n 
E 

3 

z 
c 

a> 

"5 
m 



cs 
o 

cL 

< 



TO-3 Package 

Mounting Joint 
0.250" Max 



Belleville Washer ■ 



5/16 Full Nut 
or 

5/16Locknut ■ 






i „ 


ii 




□ i 




i i 




Tf, — ? 


h — 
iL 1 





■ 6-32 Pan Head 

Teflon Sleeves 

Heat Sink 

■ 0804MC Socket 

No. 6N Washers 



■CCD 



ntn 



FIGURE 1 A. High Power Application Using 0804MC Socket. 



1992 Burr-Brown Corporation 



AB-037 



Printed in U.S.A. March, 1992 



TO-3 Package 



Mounting Joint 




6-32 Pan Head 



TTT 



I III I III I 8 I I i I ) 



Heat Sink 



Sync Nut 11 




Printed Circuit Board 



FIGURE IB. Low Power Application Using Printed Circuit Board. 



achieve low thermal resistance*". The Belleville washer does 
not bottom out and therefore can absorb the thermal expansion 
of the package® or any slight compression of the socket 
material that may occur over time. An excellent variation of 
the conical washer is called the Sync Nut™ and is available 
from EG&G Wakefield. It includes a spring washer as part of 
the nut. 

The Belleville washer should be installed on the board or heat 
sink side of the fastener, not on top of the package flange. 
Install the large face of the Belleville washer toward the 
mounting surface. When tightening against a board or 0804MC 
socket, install an additional N0.6N (narrow) flat washer 
against the relatively soft material to insure that the Belleville 
washer functions correctly. Tighten the fasteners slowly, and 
alternate between them until both are tighten to the specifica- 
tion. 

The recommended tightening torque is 6 inch-lbs., with an 
acceptable range of 4 - 7 inch-lbs. ( 0.45 - 0.79 N-m ). 

Avoid contaminating the fastener threads with thermal grease 
since it can change the torque readings. Over-tightening the 
fasteners can damage the package or internal substrate, under- 
tightening can lead to poor thermal performance. Re-torquing 
may be required after environmental screening operations 
such as bum-in. For permanent installation, an all-metal 
locknut is preferred. Don't use locknuts with plastic inserts. 

TO-3 HOLE PATTERN 

A good mounting joint between the TO-3 package and the heat 
sink requires a properly machined mounting hole pattern. 
Never drill out a single (large diameter) clearance hole for the 
package pins. Drill individual holes for each pin. Follow the 
TO-3 hole pattern illustrated in Figure 2. For best thermal 
performance, use a minimum hole size of 0.073 inch (#49 
drill). Smaller holes could interfere with the glass seal around 
each pin. 





BEST 


ACCEPTABLE 


NOT 
RECOMMENDED 


Material 


Stainless 
Steel 


Plated 
Steel 


Brass, Plastic 


Fastener Head 


Pan 


Round, 
Hex 


Binding, Flat, 
Oval, Truss, 
Fillister, Socket, 
Hex Washer 


Washers 


N0.6 Belleville 1 ' 1 
+ 

N0.6N Flat 


N0.6N Flat 




Nut 


5/16" Full, 
Sync Nut™ 


1/4" Hex 
Threaded, 
1/4" Full 




Locking Device 


5/16" LocknuF 2 ' 


Split Ring 131 


Star Washer 


NOTES: (1 ) Recommended N0.6 Belleville washer is available from ASMCO 
(part number 24087; diameter 0.31 2"; rated 78lbs initial force). (2) For high 
power use all metal type, elastic inserts not recommended. (3) Not recom- 
mended for high power or temp cycling conditions. 



TABLE I. 6-32 Fastener Hardware. 

To avoid shorting the pins to the heat sink, use #18 Teflon 
tubing to sleeve all pins. Make sure the sleeve length is slightly 
less than the thickness of the heat sink. Most pre-drilled heat 
sinks use larger 3/32 (0.094") holes for the pins, and sleeving 
is not required so long as a socket or PC board pattern is used. 
You may still want to sleeve at least two opposite pins to help 
center the package. When wiring directly to the pins, all pins 
should be sleeved, regardless of the hole size used. 

A word of caution concerning anodized heat sinks. Unless you 
know what type of anodizing was used, do not trust the 
anodizing to provide electrical insulation. Refer to the section 
called "Heat Sink Surface Treatment" for more information. 

MOUNTING SURFACE PREPARATIONS 

In general, the heat sink mounting area should have a flatness 
and finish comparable to that of the TO-3 package. When 



231 






NUMBER 


HOLE SIZE 


RECOMMENDED 


HOLE TYPE 


REQUIRED 


Mlh 


l/MAX 


DRILL SIZE 


Mounting 


2 


.147" 


.157" 


24 


Pin 


8 


.073 


.094 


46 


Thermocouple 


Optional 


.067 


.070 


51 



FIGURE 2. TO-3 Hole Pattern. 



using thinner, low power heat sinks, it is sufficient that the 
mounting area appears flat against a straight edge. When 
mounting on thicker material, surface flatness is important 
not only for thermal performance, but to avoid distorting and 
stressing the package base when it is tightened down. 

HEAT SINK SURFACE FLATNESS AND FINISH 

JEDEC recommends a surface flatness of 0.004 inch/inch 
max. The standard flatness tolerance for most extruded heat 
sinks is 0.004 inch/inch, maximum, which results in typical 
values closer to 0.002 inch/inch. Surface finish is normally 
specified around 60 micro-inches (rms). Testing has shown 
that this is acceptable for most high power applications"'. It 
is a good practice to polish the mounting area with No. 000 
steel wool, followed by an acetone or alcohol rinse, imme- 
diately prior to assembly. 

For best thermal performance, the mounting area of the heat 
sink can be spot faced. This removes oxidation or anodiza- 
tion and improves the surface flatness and finish. When 
using thermal pads instead of thermal grease, a surface 
flatness of 0.001 inch/inch is recommended. When mount- 
ing the TO-3 package to panels, brackets, or other structural 
members of the system, spot facing may be required to insure 
the proper flatness and finish. 



HEAT SINK SURFACE TREATMENT 

The typical surface treatment for aluminum heat sinks is black 
anodized <4) per MIL-A-8625, Type LT. This surface treatment 
prevents corrosion and maximizes thermal performance. Do 
not trust this surface treatment to provide electrical insulation. 
For electrical insulation, always specify hard anodized, 0.001 
inch thick, per MIL-A-8625, Type III. This file hard surface 
treatment resists scratches and punctures, and is typically 
rated for 200VDC electrical insulation for a 0.001 inch thick 
treatment. 

HEAT SINK THRU-HOLES 

Be wary of heat sinks with punched, rather than drilled, thru- 
holes. If not properly done, the area around each punched hole 
can be depressed into a crater with a raised lip or mound on the 
opposite side. This irregular surface can significantly degrade 
thermal performance. 

For high power, extruded heat sinks, the general practice is to 
drill the hole pattern. All holes should be de-burred. The holes 
for the TO-3 pins should not be chamfered too deeply, as this 
will reduce the contact area of the mounting joint. Unless 
special precautions are taken, threading the TO-3 mounting 
holes is not recommended. The threading process can also 
leave a raised mound around each hole. Threading the mount- 



MOUNTING THERMAL RESISTANCE 

Even if all of the proper mounting preparations are followed, 
the thermal resistance at the mounting joint will consist 
largely of small air gaps. Only a small percentage of the 
mounting area will actually have metal-to-metal contact. To 
minimize the thermal resistance, these gaps must be filled 
with a stable, thermally conductive material. Table II 
describes the common thermal fillers available and the 
performance that can be expected. Note that the tightening 
torque of the mounting fasteners also affects thermal perfor- 
mance (5) . 



DESCRIPTION 


(°C/W) 


APPLICATION 


HEAT SINK 
FLATNESS 
REQUIREMENTS 


Bare Joint 


0.5 - 1.0 


Low power only 


Very sensitive to 

variations in 
flatness and finish 


Thermal Grease 


0.1 - 0.2 


High Power 


Not sensitive, 
standard .004 
inch/inch (max) ok 


Aluminum Foil 1 " 
(pre-coated with 
alumina filled 
silicone) 


0.2 - 0.4 


High Power 


For lowest CH , 
.001 inch/inch (typ) 
recommended 


Aluminum Foil' 21 
(pre-coated with 
thermal grease) 


0.2 - 0.4 


High Power 


For lowest OH , 
.001 inch/inch (typ) 
recommended 


Kapton™ 
(pre-coated with 
thermal grease) 


0.3 - 0.5 


Electrical 
Insulation 


For lowest 9 CH , 
.001 inch/inch (typ) 
recommended 


Silicon Rubber 
(compressible) 


0.4-1.0 


Electrical 
Insulation 


See Text 


Mica (bare) 

Mica (with 
thermal grease) 


1.0-1.5 
0.3 - 0.4 


Electrical 
Insulation 


Not recommended 
Mica is brittle and 
prone to crack 


NOTE: (1 ) Available from BERGQUIST, part number QII-88 (with .094 inch 
holes). (2) Available from Power Devices, part number AL-1 55-100 (3) 
Available from Crayotherm, part number TO-3-8 CR2-MT. See Appendix for 
manufacturers listings. 



TABLE II. Thermal Interface Options For TO-3 Packages. 

Understanding the thermal model of the system will enable 
you to make the best mounting compromises. Consider the 
simplified thermal model in Figure 3. The mounting thermal 
resistance is represented as CH (case-to-heat sink). The over- 
all thermal resistance is represented by JA (junction-to-ambi- 
ent). For low power applications, M can be as high 30°C/W. 
In this case, the mounting thermal resistance is not a signifi- 
cant portion of the overall thermal resistance. For high power 
applications, JA can be as low as 1°C/W. Then it is critical to 
obtain a low CH . For example, at a power dissipation of 50W, 
an additional 0.5°C/W mounting thermal resistance will 
increase the junction temperature by 25°C. 



TO-3 package bare against the heat sink. For high power 
applications, this is not recommended, even if the extra 
thermal resistance is acceptable. This is because the thermal 
resistance of a bare joint can vary greatly depending on the 
surface flatness and finish of the heat sink. 

THERMAL GREASE 

For the lowest CH , thermal grease should be used in conjunc- 
tion with a properly machined and finished mounting surface. 
This combination will result in a CH of about 0. 1 °C/W. Using 
the proper fastener hardware is critical for maintaining this 
low thermal resistance over time and temperature. 

There are many suppliers of thermal grease (also known as 
heat sink compound). Thermal grease is a formulation of fine 
zinc oxide or other thermally conductive, electrically insulat- 
ing, particles in a silicone oil or other synthetic based fluid. 
The shelf life for most thermal greases is indefinite when kept 
sealed in its container, but over time, the oil may separate out. 
Mixing the components back together before use will restore 
the thermal properties. 

Thermal grease should not be applied in excess, the objective 
is to fill the air gaps, not decrease the amount of metal-to- 
metal contact. Slight rotation of the TO-3 package against the 
heat sink will promote even spreading. With the correct 
amount applied and the fasteners properly torqued, a very 
small bead of thermal grease should appear around the perim- 
eter of the TO-3 package. Although the grease may dry up over 
time, this does not degrade the thermal resistance provided the 
mounting joint remains tight. 



where 

9 JA " ^JC + 6 CH + e HA 




Ambient Air 



Range of Thermal 
Resistance Values 
(°C/W) 



0.8-5 



0.1 -1 



0.3 - 30 



/777 



FIGURE 3. Simplified Thermal Model. 



233 



THERMAL PADS 

Thermally conductive pads offer a cleaner, simpler method 
for improving the thermal interface. The lowest CH attainable 
using a thermal pad is about 0.2°C/W, which is almost as good 
as thermal grease. However, one should approach with 
caution the multitude of different materials, designs, and 
applications for thermal pads. 

Basically there are two types of thermal pads, electrically 
insulating and electrically conductive. Electrically insulating 
pads are designed to be used with discrete transistor TO-3s, 
which do not have an electrically isolated package. In general, 
they do not provide a low enough 6 CH for high power use 
because a dielectric layer must be sandwiched into the pad. 
Hybrid TO-3s with isolated headers do not require electrically 
isolated pads. They can use electrically conductive pads. 
Without the need for a dielectric layer, a very low 6 CH can be 
achieved, almost as good as thermal grease. 

While they do a good job of filling small air gaps, all thermal 
pads suffer the same problem when used against heat sinks 
with standard flatness tolerances of 0.004 inch/inch. They do 
not flow to conform with the surfaces as does thermal grease. 
Therefore, it is recommended that whenever thermal pads are 
to be used, the mounting area should be spot faced to a typical 
surface flatness of 0.001 inch/inch. Silicon rubber pads are 
also sensitive to surface flatness (6) . Approach these with 
caution. Most do not improve thermal performance over a 
bare joint. The compressibility of these rubber pads can cause 
the package header to flex and possibly crack the internal 
substrate. They can also settle over time and temperature, 
resulting in loose fasteners and low mounting pressure. 

SUGGESTED MOUNTING SCHEMES 

The mounting schemes presented here address the more 
common operating conditions for TO-3 power products (see 
Figure 4). These conditions include high power operation, low 
power operation, and functional testing under unloaded, qui- 
escent conditions. The options are for the 0804MC socket, 
individual cage jacks, and direct PC board soldering. 
Table HI describes the recommended cage jacks. 



MANUFACTURER 


PART 
NUMBER 


DRILL SIZE 
INCHES (NUM) 


COMMENTS 


Cambion 


450-3716-01-03 


.076 48 


Knock-out 
bottom permits 
wave soldering. 


Concord 


09-9047-1-03 


.104 37 


Heavy duty, 
open ended. 


SPC 

Technology 


MC76 


.089 43 


PC board 
press fit. 


Mil-Max 


0325-0-15- 
01-34-27-10-0 


.089 43 


Closed end, 
accepts full 
pin length. 


(See Appendix for manufacturers listings) 



TABLE III. Recommended Cage Jacks. 



FUNCTIONAL TESTING AND 
NO-LOAD CHARACTERIZATION 

For functional testing and no-load characterization at room 
temperature, heat sinking may not be required. These mount- 
ing schemes are the least critical and easiest to fabricate. When 
using the 0804MC socket, the socket can be mounted directly 
to the test box or PC board by drilling a single clearance hole 
for all eight socket contacts. The hole should be (0.63 - 0.75) 
inches in diameter. Be careful not to short the copper cladding 
or metal box to any of the contacts. The socket body should be 
mounted using flat head machine screws. For electrical insu- 
lation, nylon flat head machine screws may be used instead. 
When using cage jacks, follow the TO-3 hole pattern illus- 
trated in Figure 2. Use close ended cage jacks whenever 
possible to avoid solder contamination. 

LOW POWER OPERATION 

The mounting schemes for low power applications are an 
extension of those used for functional testing and no-load 
characterization. The difference is that a small heat sink is 
must be attached to the TO-3 package. The overall thermal 
resistance (0, A ) for low power applications can be relatively 
high, from 5 - 30°C/W. Therefore, CH is not as critical as for 
high power operation. In most instances, the TO-3 package 
can be mounted bare. 

Low power heat sinks are usually stamped rather than ex- 
truded, and some even press fit around the TO-3 cover. They 
are called "low power" or "standard" heat sinks ( versus "high 
power" or "extruded" heat sinks used for high power opera- 
tion ). The thermal resistance of these types of heat sink range 
from 3 - 20 °C/W, depending on their size, weight, and design. 

Low power mounting schemes are commonly used on PC 
board applications. For these applications, heat sink manufac- 
turers have developed many custom accessories such as wave 
solderable fasteners and thermally conductive pads. These 
must be approached with caution. It is important to follow the 
specific recommendations of this bulletin. Thermal pads are 
discussed in the section called "Thermal Mounting Resis- 
tance". 

The recommended fastener for PC board applications is the 
Sync Nut™. This fastener allows the TO-3/heat sink combi- 
nation to be wave soldered directly to the board. Re-torquing 
should be performed after any wave solder. For low power 
applications that do not involve temperature cycling, split ring 
lock washers may be safely used. 

HIGH POWER OPERATION 

Mounting schemes for high power operation involve the use 
of larger, heavier heat sinks, that are machined rather than 
stamped. Their size and weight usually requires that they be 
integrated into the system layout, rather than simply attached 
to the TO-3 package. In general, they are cut to length from 
extruded sections, thus are often called "extruded" heat sinks. 



Metal Box 
or PC Board 




PC Board 



Clearance Hole 
for Socket Contacts 



Split Ring 
Lockwasher 



Cage Jacks: Cambion PN 450-3716-01-03 
(For complete listing see Table III). 



No-Load Applications: PD < 3W (9 C a: 30°C/W) 



1/4 Hex 




Low-Power Applications: PD < 25W (6 H a: 3-20°C/W) 



Max Heat Sink 
Thickness 
0.250 Inches 



Teflon Sleeves 

-I 



6-32 
Pan 
Head 

_ Heat _ 

sink ^\ ,r^p 



0804MC 
Socket 



3 [ 



Belleville 
Washer 

• Lockout ■ 



Teflon Sleeves 

7h 




i 



\ ( 



W/////////M 



PC Board 



Cage Jacks: Cambion PN 450-3716-01-03 
(For complete listing see Table III). 



High-Power Applications: PD < 125W (8ha: 0.4-3°C/W) 



FIGURE 4. TO-3 Mounting Examples. 



The thermal resistance of these types of heat sink range from 
0.4 - 3°C/W for operation in still air. With forced air, «9 HA can 
be reduced by one-half to two-thirds. 

For high power applications, the overall thermal resistance 
(6 !A ) can be as low as 1°C/W. Under these conditions, obtain- 
ing a low CH is critical. To insure a good mounting joint, use 
the recommended fastener hardware and surface preparations 
as described in the previous sections of this application 
bulletin. 

THERMAL MEASUREMENT AND EVALUATION 

It is always a good idea to check the TO-3 mounting scheme 
by measuring the package case temperature (T c ) under actual 
operating conditions. The semiconductor junction tempera- 
ture (Tj) can then be calculated from the case temperature, as 
indicated in Figure 3 : 

T J= T c + PD.0 JC 

where PD is the total power dissipation (including quiescent 
power) and 9 JC is the junction-to-case thermal resistance 
(given in the product data sheet). The calculated junction 
temperature should be less than the maximum allowable 
temperature indicated by the product data sheet (typically 
150°C). 

The true case temperature is located directly below the sub- 
strate and centered within the package pins (see Figure 5). 
This location, called the case backside, will also give the most 
repeatable measurements. To directly access the case back- 
side, drill the heat sink with the optional thermocouple hole m 
as illustrated in Figure 2. The recommended thermocouple is 



an Omega fast-response probe (part no. SDX-SET-RT-K- 
SMP). Allow enough time for the system to reached thermal 
equilibrium. A touch of thermal grease on the probe tip will 
ensure good thermal contact. 

The package case temperature can also be estimated by fitting 
a spade-lug type thermocouple under the head of the mounting 
fastener. This will give the temperature at the mounting flange 
of the package rather than the case backside. The case back- 
side will actually be hotter than the mounting flange. The 
difference can be as large as 10°C, depending on the power 
dissipation, mounting thermal resistance, etc. For high power 
applications, it is recommended that the case backside tem- 
perature be measured directly, at least for the prototype setup. 

References: 

( 1 ) Thermalloy catalog #90-HS- 1 1 (page 1 3), Figures 6 and 8. 

(2) EG&G Wakefield catalog, printed 4/90 (page 103), "1 15, 
1 16, 1 17, & 1 18 Series SyncNut". 

(3) Thermalloy catalog #90-HS- 1 1 (page 1 2), "Test Results". 

(4) Thermalloy catalog #90-HS-l 1 (page 9), "Available 
Finishes". 

(5) Thermalloy catalog #90-HS- 1 1 (page 1 3), Figures 6 and 8. 

(6) Thermalloy catalog #90-HS-l 1 (page 106), "Test Method 
Comparison — TO-3 Silicon Rubber Insulators". 

(7) The optional thermocouple hole will not increase the 
mounting thermal resistance significantly. The differ- 
ence cannot be measured experimentally. Computer simu- 
lations indicate an increase of less than 0.02°C/W. 




Thermocouple 
(Spade-lug) 



Junction Temp 
(Tj) 



Backside Case Temp 




Heat Sink 



-Thermocouple Hole 
(Drill size #51) 



Thermocouple 

(Omega fast response 
PN: SDX-SET-RT-K-SMP) 



FIGURE 5. Package Case Thermal Measurement. 



MANUFACTURER 


TO-3 
SOCKET 


GAGE 
JACKS 


THERMAL 
GREASE 


THERMAL 
PADS 


HEAT 
SINKS 


TEFLON 
TUBING 


FASTENER 
HARDWARE 


TEMP 
MEAS 


ASM 

TOOLS 


BURR-BROWN 


0804MC 


















CTI 


X 


















CONCORD 




X 
















Cambion 




X 
















Mill-Max 




X 
















NEWARK 




X 






X 




X 






Thermalloy 






X 




X 










AAVID Engineering 






X 




X 










EG&G Wakefield 






X 




X 




X 






BERGQUIST 








X 












Power Devices 








X 












Crayotherm 








X 












Alpha Wire 












X 








SPC Technology 












X 








McMASTER-CARR 














X 




X 


ASMCO 














X 






OMEGA 
















X 





TABLE IV. Sources of TO-3 Mounting Hardware. 



Alpha Wire Corp. 


CONCORD 


NEWARK Electronics 


7 1 1 Lidgerwood Ave. 


30 Great Jones St. 


4801 N. Ravens wood Ave. 


Elizabeth, NJ 07207-071 1 


New York, NY 10012 


Chicago, IL 60640-4496 


(908) 925-8000 


(212) 777-6571 


(312) 784-5100 


ASMCO 


Crayotherm Corp. 


OMEGA 


19 Baltimore St. 


1185N. Van Home Way 


One Omega Drive 


Nutley,NJ07110 


Anaheim, CA 92806 


P.O. Box 4047 


(201)661-2600 


(714)630-2696 


Stamford, CT 06907 






(203) 359-1660 


AAVID Engineering, Inc. 


CTI Technologies, Inc. 




One Kool Path 


7855 E. Evans Road, Suite A 


Power Devices 


P.O. Box 4000 


Scottsdale, AZ 85260-341 1 


27071 Cabot Road, Bldg. 114 


Laconia, NH 03247 


(602) 998-1484 


Laguna Hills CA 92653 


(603) 528-3400 




(714) 582-6712 




EG&G Wakefield 




BERGQUIST 


60 Audubon Road 


SPC Technology 


5300 Edina Industrial Blvd. 


Wakefield, MA 01880 


4801 N. Ravens wood Ave. 


Minneapolis, MN 55435 


(617) 245-5900 


Chicago, IL 60640 


(612) 835-2322 




(312)907-5181 




McMASTER-CARR 




Cambion Division 


P.O. Box 54960 


Thermalloy, Inc. 


MIDLAND ROSS 


Los Angeles, CA 90054-0960 


2021 W. Valley View Lane 


One Alewife Place 


(213) 692-5911 


P.O. Box 810839 


Cambridge, MA 02140 




Dallas, TX 75381-0839 


617)491-5400 


Mill-Max Mfg. Corp. 


(214) 243-4321 




P.O. Box 300 






190 Pine Hollow Road 






Oyster Bay, NY 11771-0300 






(516) 922-6000 





The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes 
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change 
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted toany third party. BURR-BROWN does not authorize or warrant 
any BURR-BROWN product for use in life support devices and/or systems. 



BURR BROWN APPLICATION BULLETIN 237 

Burr-Brown Corporation • Mailing Address: PO Box 11400 Tucson, AZ 85734 • Tel: (602) 746-1111 • FAX: (602) 746-7401 



IMMI 



OPERATIONAL AMPLIFIER AND 
INSTRUMENTATION AMPLIFIER MACROMODELS 



By Hubert Biagi and R. Mark Stitt 
Edited by Bonnie Baker 



INTRODUCTION 

This application bulletin and the accompanying disk is a 
collection of Spice models for Burr-Brown op amps, differ- 
ence amps, and IAs. There are three types of models; a 
standard macromodel, an enhanced macromodel and a 
simplified circuit model. The standard op amp macromodels 
were derived using the MicroSim Corporation PSpice® Parts™ 
Simulation software. An enhanced version of this standard 
macromodel is also included for all op amps and instru- 
mentation amplifiers. In some instances, a third model, "X", 
is available. This model is not a macromodel, but rather a 
simplified circuit model at the transistor level. The simpli- 
fied circuit models produce more accurate simulations, but 
because of their complexity, require more simulation time. 
The instrumentation amplifier macromodels use op amp 
macromodels and additional components. Table I summarizes 
how the files on this disk are labeled. 



FILE NAME 


DESCRIPTION 


OPA1 1 1 .MOD 

OPA111E.MOD 

OPA603X.MOD 

INA105.MOD 

INA105E.MOD 


OPA1 1 1 Standard Op Amp Macromodel 
OPA1 1 1 Enhanced Op Amp Macromodel 
OPA603 Simplified Circuit Model 
INA1 05 Standard Difference Amp Macromodel 
INA1 05 Enhanced Difference Amp Macromodel 



TABLE la. Examples of Files on Macromodel Disk. 



STANDARD OP AMP MACROMODELS 

The op amp macromodels were created by running the 
PSpice® Parts™ Simulation software on an IBM-compatible 
PC. This software uses the standard Boyle op amp model '. 
The PSpice manual available from MicroSim (2) contains a 
detailed discussion of each of the elements used in the 
macromodels. 

Op amp macromodels use the node assignments shown in 
Figures 1 to 3. Table II below summarizes the circuits. Figure 
4 shows the external op amp node assignments. Tables in, IV, 
and V list component prefix designations, macromodel com- 
ponent descriptions, and Spice INPUT designations. 



FIGURE 


INPUT TRANSISTORS 


TYPE OF MACROMODEL 


1A 


N-Channel JFET 


Standard PSpice* Parts™ 


1B 


N-Channel JFET 


Enhanced PSpice* Parts™ 


1C 


P-Channel JFET 


Standard PSpice* Parts™ 


1D 


P-Channel JFET 


Enhanced PSpice* Parts™ 


2A 


NPN Bipolar 


Standard PSpice* Parts™ 


2B 


NPN Bipolar 


Enhanced PSpice* Parts™ 


2C 


PNP Bipolar 


Standard PSpice* Parts™ 


2D 


PNP Bipolar 


Enhanced PSpice* Parts™ 


3A 


NPN Bipolar 


OPA620/621 Simplified Circuit Model 


3B 


Bipolar CFB 


OPA603 Simplified Circuit Model 



TABLE H. Op Amp Macromodel Circuits. 



CONTENTS OF MACROMODEL DISK 



OPA27 


OPA512 


OPA27E 


OPA512E 


INA101 


INA101E 


OPA603X 


OPA27HT 


OPA541 


OPA27HE 


OPA541E 


IMA102 


INA102E 


OPA620X 


OPA37 


OPA602 


OPA37E 


OPA602E 


INA103 


INA103E 


OPA621X 


OPA77 


OPA606 


OPA77E 


OPA606E 


INA105 


INA105E 




OPA101 


OPA620 


OPA101E 


OPA620E 


INA106 


INA106E 




OPA102 


OPA621 


OPA102E 


OPA621E 


INA110 


INA110E 




OPA1 1 1 


OPA627 


OPA111E 


OPA627E 


INA117 


INA117E 




OPA121 


OPA637 


OPA121E 


OPA637E 


INA120 


INA120E 




OPA128 


OPA1013 


OPA128E 


OPA1013E 








OPA177 


OPA2107 


OPA177E 


OPA2107E 








OPA404 


OPA21 1 1 


OPA404E 


OPA2111E 


UAF42 


UAF42E 




OPA445 


OPA2541 


OPA445E 


OPA2541E 








OPA501 


OPA2604 


OPA501E 


OPA2604E 








OPA51 1 




OPA511E 











o 

CM 
i- 

o 
E 

3 



3 
CD 

C 

o 

o 

a. 
a. 
< 



TABLE lb. Contents of Macromodel Disk. 

1) For more information, see: G.R. Boyle. B.M. Conn, D.O. Pederson, and J.E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE Journal 
of Solid-State Circuits, SC-9, 353 (1974). 

2) MicroSim Corporation, 20 Fairbanks, Irvine, CA 92718 USA, (714) 770-3022, (800) 245-3022. 
PSpice* Pans™- MicroSim Corp. 



1990 Burr-Brown Corporation 



AB-020B 



Printed in U.S.A. October, 1991 



IN „„ LN 



- R D2 R P > A D P 



11 



+ln O- 



C, 



12 



-In O « » rj1 J2 

r 



See Table IV, for a more 
detailed description of 
thee 



10 




92 



-till* 



T 



-o v+ 



^02 " 

99 



Dlp V lp 

V L1M 

T — ' I • — 2 — VW^- 

r~ —1— a 



— v c 

53 



CP' 



J 



R 2 ; 



Ml JL~ 

CP ® 



E GND 

X 



- v„ 



X X 



-ov„ 



54 



— V E 



-O V- 



FIGURE la. N-Channel JFET-Input Op Amp Standard PSpice® Parts™ Macromodel. 



^di ^ R D2 ; 
c, 



11 " — II — " 12 



+in o 



-ln O- 

^2CM 



oi L <j>« 



» K - 



X 



-o v+ 



'1CM I 



J1 J2~U- 



10 



Rqj. 

99 



T. 



^SS > -i- ^SS 



J 



Dlp V lp 

— i— HHi — 

C 2 __. R i 



— V c 
53 



CP $ 



■ E GN0 



X Of. X _L ± 



-ov n 



54 

+ 

— V E 



I 



-O V- 



02 22 VQ2 



See Table IV, for a more detailed 
description of the components. 



F A 1 N ■ i J i — i 



v Q , 



FIGURE lb. N-channel JFET-Input Op Amp Enhanced PSpice® Parts™ Macromodel. 



+ln O- 



3 f 



10 



-In O- 



►Hi 

C, 

11 ' 1| 1! 12 



See Table IV, for a r d 
more detailed 
description of the 
components. 



"r. i — n ■ i hh -v c 



T 



-o v+ 



53 



LP V LP 







v LIM 

-t— HHi — t-W 

R01 



-ov„ 



G CM, 



E GND 

-X- 



9J 
1+ 

— V B 

JL _L JL 



CD 0) 



54 

+ 



J o 



FIGURE lc. P-channel JFET-Input Op Amp Standard PSpice® Parts™ Macromodel. 



'S3© 



+ln O- 



-In O- 



C 2CM 



I 



10 



J1 J2 



11 



12 

:r 



jl r 



T 



-o v+ 



^-w^iih-ri 



D LP 



"LP 




— v c 

53 



Rrn 



3)0 



-ov„ 



54 



I 



-O V- 



See Table IV, for a more detailed 
description of the components. 



<-as 



02 ^ , V Q2 




^i|3tL 



-"01 v Q1 



FIGURE Id. P-channel JFET-Input Op Amp Enhanced PSpice® Parts™ Macromodel. 



11 



+ln O- 



C, 



.R C2 R, 



12 



p^ ]t Dp 





T 



-o v+ 



— v c 



53 



-OV Q 



54 



I 



-O V- 



See Table IV, for a more detailed 
description of the components. 



FIGURE 2a. NPN-Input Op Amp Standard PSpice® Parts™ Macromodel. 



ENHANCED PSpice® Parts™ MACROMODEL 

The enhanced version of the standard PSpice® Parts™ model 
contains the following additions and changes: 

Input capacitance 

Differential and common-mode input capacitors, C D|F , C 1CM , 
and C 2CM have been added to the standard macromodel. 
Input capacitance could also be modeled by including ca- 
pacitor coefficients in the transistor models. Instead, discrete 
capacitors were used so the comparison to the standard 
model would be more obvious. 



Input protection diodes 

If an op amp contains input protection diodes, its enhanced 
op amp macromodel also contains diodes connected be- 
tween the input pins as shown in Figures 4C and 4D, for 
example. 

Quiescent power 

R p was replaced by R Q . The value of R Q is higher. It models 
only the resistive portion of quiescent current. The current 
sources described below model the constant portion of the 
quiescent current. This technique provides a more accurate 
model of quiescent current vs power-supply voltage. 



from the Power-Supply Nodes 

A number of components were added so that both load and 
quiescent current flow from the power supply nodes. 

FQ3 mirrors the current flowing from VLIM. 
Positive current from FQ3 flows through DQ1 into VQ1. 
Negative current from FQ3 flows through DQ2 into VQ2. 
FQ1 supplies constant portion of IQ plus mirrors positive 

output current which is measured by VQ1. 
FQ2 supplies constant portion of IQ plus mirrors negative 
output current which is measured by VQ2. 
NOTE: The enhanced op amp macromodels are more com- 
plicated and require more simulation time than the 
standard macromodels, but will provide more accu- 
racy in simulations in some applications. 

DUAL AND QUAD OP AMPS 

All op amps are modeled as single devices. To model duals 
or quads, use two or four models. Quiescent current for the 
dual or quad op amp macromodel is the dual or quad op amp 
quiescent current divided by two or four. 

INSTRUMENTATION AMPLIFIERS 
AND DIFFERENCE AMPLIFIERS 

Instrumentation amplifier and difference amplifier 
macromodels use standard op amp macromodels plus addi- 
tional components as shown in Figures 5 to 9. There are two 
types of models used for difference amplifiers. They are the 
four-resistor difference amplifier and the five-resistor dif- 
ference amplifier. 



The four-resistor difference amplifier macromodel, used for 
the INA105, INA106, and the difference amplifier section in 
all instrumentation amplifier macromodels, is shown in 
Figure 5. The circuit uses and op amp and four matched 
resistors. If Rj/R, = R/R3, GAIN = R/R, and CMR = °°. To 
simulate DC CMR error, Rj is set 0.01% low. CMR for a 
four resistor difference amplifier is: 

CMR = -20 LOG10 [(%/100) • R/(R, + RJ] 

Where: 
% = % error in any resistor. 

With a 0.01% resistor error, DC CMR for the INA105 unity 
gain difference amplifier is 86dB, and DC CMR for the 
INA106 gain-of-ten difference amplifier is 100.8dB. 

To simulate AC CMR error, a small value capacitor, C 2 , is 
placed in parallel with R 2 to roll-off of CMR with increasing 
frequency. 

FIVE-RESISTOR DIFFERENCE AMPLIFIER 

The five-resistor difference amplifier macromodel used for 
the INA1 17 is shown in Figure 9. The advantage of the five- 
resistor difference amplifier configuration is a boost in input 
common-mode-voltage range for a given op amp common- 
mode range. The circuit uses an op amp and five matched 
resistors. If (Rj II R 5 )/R, = R 4 /R 3 , GAIN = R./R, and CMR = 
°°. To simulate DC CMR error, R. is set 0.005% low. For 
errors in R 4 , the CMR for a five-resistor difference amplifier 
is; 

CMR = -20 LOG10 [(%/100) • R,/(R, + R 4 )] 




FIGURE 2b. NPN-Input Op Amp Enhanced PSpice® Parts™ Macromodel. 



Where: 
% = % error in R, 
*R 2 IIR 5 = R 2 «R 5 /(R 2 +R 5 ) 

With a 0.005% resistor error, DC CMR for the INA1 17 high 
common-mode-voltage unity-gain difference amplifier is 
86.5dB. Note that unlike the four resistor difference ampli- 
fier, the sensitivity of DC CMR to errors in resistor value is 
different for different resistors. 

To simulate AC CMR error, a small value capacitor, C 2 , is 
placed in parallel with R 2 to roll-off of CMR with increasing 
frequency. 



LIMITATIONS 

These macromodels are intended to help designers simulate 
typical amplifier performance. The macromodels were com- 
piled by entering data sheet typical specifications into 
MicroSim Parts™. Where data sheet specifications were not 
available, typical measured values or design values were 
used. Macromodels were verified with several standard 
simulations such as gain-phase and large and small-signal 
transient response. In some cases adjustments were made to 
the Parts™ macromodel inputs or component parameters so 
simulations with the macromodel more closely agreed with 
actual measured typical performance. 



Q) 




-o v+ 



10 



+ln o- 



r ei: 

13 



14 



-In 



O— • £jai Q2^j — 



11 

^C2 " 



c, 



12 

■ R C2 



r H|l H% h jM l |_b r 



->lp 

Vlim 

7 8 




53 
D c 



-ov„ 



54 



— V E 



I 



-O V- 



See Table IV, for a more detailed 
description of the components. 



FIGURE 2c. PNP-Input Op Amp Standard PSpice® Parts™ Macromodel. 



Dp A 



+ln O- 



-In O- 



C 2CM 





-o v+ 




R 01 



CP (D 



E GND 



JL Of." J. _L 



-OV n 



' 54 
+ 

— V E 



I 



-O V- 



See Table IV, for a more detailed 
description of the components. 



r 



F03 



°01 V Q1 




FIGURE 2d. PNP-Input Op Amp Enhanced PSpice® Parts™ Macromodel. 



Since these macromodels only simulate the typical perfor- 
mance of certain selected specifications, they will not pre- 
dict actual device performance under all conditions. Good 
design practice dictates that, in addition to simulation with 
macromodels, circuit verification must include; 1) Worst 
case analysis with data sheet minimum and maximum room 
temperature specifications, 2) Worst case analysis with 
variation of specifications over the operating temperature 
range, 3) thorough breadboard evaluation, and 4) complete 
prototype characterization. 

EFFECTS THE STANDARD 
MACROMODEL SIMULATES 

The standard macromodel simulates the following effects: 1) 
DC input impedance and bias current, 2) differential and 
common-mode gain, 3) open-loop gain and phase vs fre- 
quency (2 poles only), 4) output slew rate limiting and 
output resistance, 5) output voltage and current limiting, and 
6) DC quiescent power drain. 



EFFECTS THE STANDARD 
MACROMODEL DOES NOT SIMULATE 

Some of the characteristics the standard macromodel does 
not simulate are: 1) distortion, 2) output current flowing 
from the power supplies, 3) noise 4) variations in perfor- 
mance vs temperature. 5) "Worst case" specifications (e.g. 
V os , I QS , etc.), 6) Zeros in the gain-phase response, 7) more 
than 2 poles in gain-phase response. 

EFFECTS THE ENHANCED 
MACROMODEL SIMULATES 

The enhanced version of the standard PSpice R Parts™ model 
simulates the standard effects and, in addition, simulates: 1) 
quiescent current and output load current flowing from the 
power-supply pins, 2) input capacitance, 3) input protection 
circuitry where applicable. 



250£1- 



10 



+ln O- 



.250i2 




Q2 



2X 



-In O- 



11 



2X 



18 



12 



R 4 

35£i li (V) 



13 



Q3 



06, 



19 



15 



20 



2X 



Q4 Q9 



4X 
14 



16 



2X 
22 



21 



:62.5£J 250£1 




f 8 "a '. 

250Q 250£J- 



'CP 



25 



-O V+ 



^13 
40X 



Q11 



20X 

— Q12 



20X 



24 



0) 



40X 

fa 14 



-O V- 



NOTE: OPA620 and OPA621 simplified-circuit 
are the same with the following exceptions. 





c, 








MODEL 


(PF) 


(mA) 


(mA) 


(mA) 


OPA620 


10 


1.1 


4 


2 


OPA621 


2 


1.3 


3.5 


3.5 



FIGURE 3a. OPA620 and OPA621 High Speed Op Amp Simplified-Circuit Macromodel. 



243 



♦In 



-In O- 



R 0B 





CD 1 



28 



C B -r- > R B R 




-o v+ 



23 




-OV 



21 



25 



27 n 

_T_ 



-o v- 



FIGURE 3b. OPA603 High Speed Current-Feedback Op Amp Simplified-Circuit Macromodel. 




FIGURE 4a. Op Amp Macromodel Node Assignments. 



SIMULATING OP AMP INPUT 
NOISE AND OFFSET 

To simulate op amp input voltage noise, current noise, 
voltage offset, and current offset, error sources can be 
inserted as shown in Figure 4B. 



G N2\ 

-In O- 



v+ 

o 



G os(T) 

+ ln O— J— I I I hp ■ I I k-? 

n /'TN e n E °s 




V- 



ERROR-SOURCE DESIGNATIONS 



-OV 



DESIGNATION 


DESCRIPTION 


Gos 


Input Bias-Current Offset 


E N 


Input Voltage Noise 


E« 


Input Offset Voltage 


G* 


+lnput Bias-Current Noise 


G N2 


-Input Bias-Current Noise 



FIGURE 4b. Recommended Connection of Macromodel 
Noise and Offset Error Sources. 



-In O- 



+ln O- 



2 , 3 

X-r\yr 



-OV n 



6 
V- 



FIGURE 4c. Input Protection Diode Circuitry Used on 
OPA27/37/27HT Enhanced Macromodels. 



!N M R 2'N. 



AAA 

-In O • fff- 




v+ 

o 



+ lnO--^M/- 



± 




FIGURE 4d. Input Protection Circuitry Used on OPA77/177 
Enhanced Macromodels. 



v+ 





2 *a 1 a 13 
-In O — • \Mr- 



+ln O — • 

1 R3 




-O Sense 



-OVo 



14 



-vW- 
r 4 



o Ref 



FIGURE 5. Difference Amp Macromodel and Node Assign- 
ments. 



D 


Diode 


E 


Voltage-Controlled Voltage Source 


F 


Current-Controlled Current Source 


G 


Voltage-Controlled Current Source 


H 


Current-Controlled Voltage Source 


J 


JFET Transistor 


Q 


Bipolar Transistor 


R 


Resistor 


V 


Independent Voltage Source or Stimulus 



TABLE HI. Macromodel Component Prefix Definitions' 3 '. 



COMPONENT 


DESCRIPTION 




Phase-Control Capacitor 


1 c 


Compensation Capacitor 




Slew-Rate Limiting Capacitor 


Dp 


Substrate Junction 




Voltage-Controlled Voltage Source 


p GND 
B 


Output Device (Controlled by the Current Through V B , 


G A 


V c , V E , and V,,,, V ) 
Interstage Transconductance (Controlled by Differential 




Voltage at the Input Device Loads) 


G CM 


Common-Mode Transconductance (Controlled by the 




Common-Mode Voltage at the Input Device Emitters 
or Sources) 


W'ss 

M UM 


Input Stage Current 


Voltage-Limiting Device 


J,. J 


JFET Input Transistors 


Q„6 2 


Bipolar Input Transistors 




Interstage Resistance 




Input-Stage Load Resistance 


R D i> R oz 


Input-Stage Load Resistance 


R E1 , R H 

R E E' R ss 


Input-Stage Emitter Resistance 


Input-Stage Current-Source Output Resistance 


"or "02 


Output Resistors 




Power Dissipation Resistor 




Independent Voltage Source 


V . Do 


Output Offset Limiter (to V+) 


V E ,D E 


Output Offset Limiter (to V-) 




Output Current Limiting Sensor 


V LN' ^ 


Negative Supply Limit 




Positive Supply Limit 



TABLE IV. Op Amp Macromodel Components* 3 '. 



BURR-BROWN 


MACROMODEL 




SYMBOL 


DESIGNATION 


DEFINITION 


V+, V- 


+Vpwr, -Vpwr 


Positive, Negative Power Supply 




+Vout, -Vout 


Max Positive, Negative Output 






Swing 


SR 


+SR 


Positive-Going Slew Rate 


SR* 


-SR 


Negative-Going Slew Rate 




Pd 


Quiescent Power Dissipation 


1. 


1. 


Input Bias Current 


A* 


Av-dc 


DC Open-Loop Voltage Gain 


UGBW 


F-OdB 


Unity-Gain Frequency 


CMRR 


CMRR 


Common-Mode Rejection Ratio 


M 


Phi 


Phase Margin at F-OdB (°) 


r o 


Ro-dc 


DC Output Resistance 


z o 


Ro-ac 


AC Output Resistance 


'so 


los 


Short-Circuit Output Current 


Co 


Cc 


Compensation Cacitance 



TABLE V. PSpice® Parts™ Inputs' 3 '. 



3) Per MicroSim Corp. PSpice*. 



245 



PRODUCT HIGHLIGHTS 
AND NOTES 

INA101 

INSTRUMENTATION AMPLIFIER 

KEY FEATURES 

Input offset voltage: 25uV max 

Input offset voltage drift: 0.25uV/°C max 

CMR: 106dB (60Hz) min 

Available packages: Hermetic Ceramic DIP, Hermetic 
Metal TO- 100, Plastic DIP, and Plastic SOIC. 
See Figure 6 for macromodel circuit diagram. 

Notes about the INA101: 

The INA101 contains internal gain-setting feedback resistors; 
R ra =20ka 

When using the metal package (TO- 100) these resistors 
must be used. When using the ceramic or plastic packages, 
the internal gain-setting feedback resistors may be used, or 
external feedback resistors may be used. 

If the internal resistors are used: 

GAIN = 1 + (40K/R o ) 

If external feedback resistors are used: 

GAIN = 1 + (2 • RJR C ) 

Where: 

R G = external gain-setting resistor (Q) 
R FB = optional external feedback resistor (Q) 
See product data sheet (PDS-454) for gain accuracy speci- 
fications. 

INA102 

INSTRUMENTATION AMPLIFIER 

Low quiescent current: 750uA max 

Internal gains: 1, 10, 100, 1000 (V/V) 

Low gain drift: 5, 10, 15, 20ppm/°C max, Gain = 1, 10, 100, 

1000 

Input offset voltage: lOOpV max 
Input offset voltage drift: 2pV/°C max 
CMR: 90dB (60Hz) 

Available packages: Hermetic Ceramic DIP, Plastic DIP, 
and Plastic SOIC. 

See Figure 6 for macromodel circuit diagram. 
Notes about the INA102: 

The INA102 contains internal gain-setting and feedback 
resistors; 

R ra =20kQ 



INA102 INTERNAL GAIN-SETTING RESISTORS 



R 

(£i) 


GAIN 

(V/V) 


4.444k 


10 


404 


100 


40.4 


1000 



o 




4 



6 



FIGURE 6. Standard Instrumentation Amplifier Macromodel 
and Node Assignments. 

The internal resistors are ratio trimmed to high accuracy and 
have excellent tracking with temperature for low gain drift. 
If the internal resistors are used: 

GAIN = 1 + (40k/R o ) 
External gain-setting resistors can be used in series with one 
of the internal gain-setting resistors. If external gain-setting 
resistors are used: 

GAIN = 1 + (40k/[R OI + R GE ]) 
R GI = One of the three internal gain-setting resistors shown 
in the table (Q) 

R GE = external gain-setting resistor (£2) 

See product data sheet (PDS-523) for gain accuracy speci- 
fications. 

IN A 103 

INSTRUMENTATION AMPLIFIER 

Low noise: InV/VHz 

Low THD: 0.002% (20Hz to 20kHz, Gain = 1 to 100) 

Wide supply range: +9V to ±24V 

High gain-bandwidth: 100MHz, Gain=1000 

Internal gains: 1, 100 (V/V) 

Input offset voltage: 100U.V max 

Input offset voltage drift: 2uV/°C max 

CMR: 1 lOdB min 

Available packages: Hermetic Ceramic DIP and Plastic 
DIP 



See Figure 7 for macromodel circuit diagram. 



Notes about the INA103: 

The INA103 contains internal gain-setting and feedback 
resistors; 

R ra =3kQ 
R G = 60.606Q (Gain = 100) 

The internal gain-setting feedback resistors may be used, or 
external feedback resistors may be used. 

If the internal resistors are used: 

GAIN = 1 + (6k/R G ) 

If external feedback resistors are used: 

GAIN = 1+ (2 • R FB /R G ) 

Where: 

R G - Optional external gain-setting resistor (Q) 
R FB = Optional external feedback resistor (Q) 

See product data sheet (PDS-1016) for gain accuracy speci- 
fications. 

INA105 

DIFFERENCE AMPLIFIER 

Gain: 1 (V/V) 

Gain error: 0.01% max 

Low nonlinear ity: 0.001% max 

CMR: 86dB min over temp 



Available packages: Hermetic Metal TO-99, Plastic DIP, 
and Plastic SOIC. 

See Figure 5 for macromodel circuit diagram. 



INA106 

DIFFERENCE AMPLIFIER 

Gain: 10 (V/V) 

Gain error: 0.01% max 

Low nonlinearity: 0.001% max 

CMR: lOOdB min over temp 

Available packages: Hermetic Metal TO-99 and Plastic 
DIP. 

See Figure 5 for macromodel circuit diagram. 
INA110 

INSTRUMENTATION AMPLIFIER 

FET input 

Bias current: 50pA max 
Internal gains: 1, 10, 100, 200, 500 (V/V) 
Low gain drift: 10 to 50 ppm/°C 
Input offset voltage drift: 2uV/°C max 
CMR: 106dB min 

Available packages: Hermetic Ceramic DTP, Plastic DTP, 
and Plastic SOIC. 



+ln O — •- 




16 



-In O— • fai 

R 



T 



— v, 



15 



17 



10 



> 1 



D, 



V+ 

o 




A, 



c 11 

R FB1 



Rl 13 



-MA 



W\A-n 



R FB2 





-ov Q 



vyv^ — m — j 



12 



V »-o Ref 

• ^1 



V- 



FIGURE 7. INA103 Current-Feedback Instrumentation Amplifier Macromodel and Node Assignments. 



247 



See Figure 8 for macromodel circuit diagram. 
Notes about the macromodel: 

The INA110 contains internal gain-setting and feedback 
resistors; 

R FB =20kn 

INA110 INTERNAL GAIN-SETTING RESISTORS 



R 


GAIN 


(") 


(V/V) 


4.4444k 


10 


404.04 


100 


201.0 


200 


80.16 


500 



The internal resistors are ratio trimmed to high accuracy and 
have excellent tracking with temperature for low gain drift. 
If the internal resistors are used: 

GAIN = 1 + (40k/R o ) 

External gain-setting resistors can be used in series with one 
of the internal gain-setting resistors. If external gain-setting 
resistors are used: 

GATN=l + (40k/[R CI +R GE ]) 

R G1 = one of the four above internal gain-setting resistors (£2) 
R GE = external gain-setting resistor (CI) 

See product data sheet (PDS-645) for gain accuracy specifi- 
cations. 



INA117 

HIGH COMMON-MODE VOLTAGE DIFFERENCE 
AMPLIFIER 

Gain: 1 (V/V) 

Gain error: 0.02% max 

Low nonlinear ity: 0.001% max 

Common-mode input range: +200V 

Input protection: ±500V common-mode or differential 

CMR: 106dB (60Hz) 

Available packages: Hermetic Metal TO-99, Plastic 8-pin 

DIP, and Plastic 8-pin SOIC. 

See Figure 9 for macromodel circuit diagram. 



2 A R A \ 13 
-In O — • 



V+ 

o 



Ref B 



+ln O — • 

1 R 3 




-ov Q 



14 



AAA RS,A 

R 4 8 



FIGURE 9. INA117 High Voltage Difference Amplifier 
Macromodel and Node Assignments. 




FIGURE 8. INA1 10 Current-Feedback FET-Input Instrumentation Amplifier Macromodel and Node Assignments. 



v+ 






6 
v- 



INA120 INTERNAL GAIN CONNECTIONS* 



GAIN 


CONNECT 


1 


G4-G5 


G14-G15 




10 


G4-G5 


G11-G14-G15 




100 


G4-G8 


G11-G14 


G10-G15 


1000 


G4-G8 


G11-G14 


G9-G15 


*"G" numbers are also package pin numbers. 



INSTRUMENTATION AMPLIFIER 

Input offset voltage: 25uV max 
Input offset voltage drift: 0.25uV/°C max 
Internal gains: 1, 10, 100, 1000 (V/V) 
CMR: 106dB (60Hz, Gain = 100) 

Available packages: Hermetic Ceramic DIP and Plastic 
DIP. 

See Figure 6 for macromodel circuit diagram. 
Notes about the INA120: 

The INA120 contains an internal gain-setting and feedback 
resistor string; 



R FB = 20kQ 

INA120 INTERNAL GAIN-SETTING RESISTORS 



[ni 


GAIN 

[V/V] 


4000 


10 


400 


100 


44 


1000 



The internal resistors are ratio-trimmed to high accuracy and 
have excellent tracking with temperature for low gain drift. 
If the internal gain-setting resistor string is used, it can be 
connected to the amplifier input terminals to give accurate 
gains of 1, 10, 100, and 1000. The gain equation is the same 
as for external gain-setting resistors, but in higher gains, part 
of the lower gain-setting resistor is added to the feedback 
resistor so the values shown for R Q can not be inserted di- 
rectly in the equation — see Figure 10. 

The internal feedback resistors can be used with external 
feedback resistors. If the internal feedback resistors are used 
with external gain-setting resistors: 

GAIN = 1 + (40k/R o ) 

Where: 

R G = optional gain-setting resistor (Q) connected between 
G5 and G14 with Gl 1 open 

External gain-setting and feedback resistors can be used. If 
external feedback resistors are used: 

GAIN = 1 + (2 • R FB /R ) 

Where: 

R G = Optional external gain-setting resistor (£2) 
R FB = Optional external feedback resistor (Q) 

See product data sheet (PDS-1071) for gain accuracy speci- 
fications. 

OPA27 

OPERATIONAL AMPLIFIER 

Low noise: 3.8nV/VHz max, 1kHz (100% tested) 
Low input offset voltage: 25uV max 
Low Input offset voltage drift: 0.6liV/°C max 
High open-loop gain: 120dB min 
High common-mode rejection: 1 14dB min 
Available packages: Hermetic Metal TO-99, Hermetic Ce- 
ramic DIP, Plastic DIP, and Plastic SOIC. 



FIGURE 10. INA120 Internal Gain-Setting Resistor 
Connections. 

See Figures 2A and 2B for macromodel circuit diagram. 
Notes about the macromodel: 

The enhanced macromodel also contains back-to-back di- 
odes across the input terminals as shown in Figure 4C. 

OPA27HT 

OPERATIONAL AMPLIFIER 

Specified for 200°C operation 

Low input offset voltage: 400llV max, 200°C 

Available packages: Hermetic Metal TO-99 

See Figures 2A and 2B for macromodel circuit diagram. 

Notes about the macromodel: 

The enhanced macromodel also contains back-to-back di- 
odes across the input terminals as shown in Figure 4C. 



OPA37 

OPERATIONAL AMPLIFIER 

Stable in gain of 5V/V or higher 

Small signal gain-bandwidth: 63MHz typ 

Slew rate: 11.9V/(is typ 

Low noise: 3.8nV/>/Hz max, 1kHz (100% tested) 
Low input offset voltage: 25|xV max 
Low Input offset voltage drift: 0.6|iV/°C max 
High open-loop gain: 1 20dB min 
High common-mode rejection: 1 14dB min 
Available packages: Hermetic Metal TO-99, Hermetic Ce- 
ramic DIP, Plastic DIP, and Plastic SOIC 

See Figures 2A and 2B for macromodel circuit diagram. 

Notes about the macromodel: 

The enhanced macromodel also contains back-to-back diodes 
across the input terminals as shown in Figure 4C. 

OPA77 

OPERATIONAL AMPLIFIER 

Low input offset voltage: 25uV max 

Low Input offset voltage drift: 0.3fiV/°C max 

High open-loop gain: 130dB min 

High common-mode rejection: 120dB min 

Quiescent current: 1 .5mA 

Available packages: Hermetic Ceramic DIP, Plastic DIP, 
and Plastic SOIC. 

See Figures 2A and 2B for macromodel circuit diagram. 
Notes about the macromodel: 

The enhanced macromodel also contains input protection 
diodes and resistors as shown in Figure 4D. 

OPA101 

OPERATIONAL AMPLIFIER 

FET input 

Low bias current: lOpA max 

Low noise: 8nV/VHz max, 10kHz (100% tested) 

Low input offset voltage: 250|iV max 

Low Input offset voltage drift: 5uV/°C max 

Available packages: Hermetic Metal TO-99 

See Figures 1A and IB for macromodel circuit diagram. 
OPA102 

OPERATIONAL AMPLIFIER 

FET input 

Stable in gain of 3V/V or higher 

Small-signal gain-bandwidth: 40MHz typ 

Slew rate: 10V/u.s 

Low bias current: lOpA max 

Low noise: 8nV/VHz max, 10kHz (100% tested) 

Low input offset voltage: 250|iV max 

Low Input offset voltage drift: 5|iV/°C max 

Available packages: Hermetic Metal TO-99 

See Figures 1A and IB for macromodel circuit diagram. 



OPA111 

OPERATIONAL AMPLIFIER 

FET input 

Low bias current: lpA max 

Low noise: 8nV/VHz max, 10kHz (100% tested) 

Low input offset voltage: 250(1 V max 

Low Input offset voltage drift: l(i,V/°C max 

Available packages: Hermetic Metal TO-99 

See Figures 1C and ID for macromodel circuit diagram. 

Notes about the macromodel: 

The OPA111 slew rate is asymmetric with the positive- 
going slope faster than the negative-going slope (4V/|is vs 
2V/ns). Since the PSpice macromodel only allows asymmetric 
slew rate in the opposite direction, a conservative symmetri- 
cal slew rate of 2V/ns was usedin the macromodel. 

OPA121 

OPERATIONAL AMPLIFIER 

FET input 

Low bias current: 5pA max 

Low noise: 6nV/VHz typ, 10kHz 

Input offset voltage: 2mV max 

Input offset voltage drift: 3jiV/°C typ 

Available packages: Hermetic Metal TO-99 and 8-pin 

Plastic DIP 

See Figures 1C and ID for macromodel circuit diagram. 
Notes about the macromodel: 

The OPA121 slew rate is asymmetric with the positive- 
going slope faster than the negative-going slope (4V/jis vs 
2V/|Xs). Since the PSpice macromodel only allows asymmet- 
ric slew rate in the opposite direction, a conservative sym- 
metrical slew rate of 2V/u.s was used in the macromodel. 

OPA128 

OPERATIONAL AMPLIFIER 

FET input 

Ultra low bias current: 75fA max 

Low input offset voltage: 500(xV max 

Low Input offset voltage drift: 5\lV/°C max 

Available packages: Hermetic Metal TO-99 

See Figures 1C and ID for macromodel circuit diagram. 

OPA177 

OPERATIONAL AMPLIFIER 

Low input offset voltage: 10u.V max 

Low Input offset voltage drift: 0.1fiV/°C max 

High open-loop gain: 130dB min 

High common-mode rejection: 130dB min 

Quiescent current: 1.5mA 

Available packages: Hermetic Ceramic DIP, Plastic DIP, 
and Plastic SOIC. 

See Figures 2A and 2B for macromodel circuit diagram. 



Notes about the macromodel: 

The enhanced macromodel also contains input protection 
diodes and resistors as shown in Figure 4D. 

OPA404 

QUAD OPERATIONAL AMPLIFIER 

FET input 

Low bias current: 4pA max 
Small-signal gain-bandwidth: 6.4MHz 
Slew rate: 35V/(0.s 

Available packages: Hermetic Ceramic DIP and Plastic 
DIP 

See Figures 1C and ID for macromodel circuit diagram. 
OPA445 

HIGH VOLTAGE OPERATIONAL AMPLIFIER 

FET input 

Wide power supply range: +10V to +45V 
Low bias current: 50pA max 

Available packages: Hermetic Metal TO-99 and 8-pin 
Plastic DIP 

See Figures 1C and ID for macromodel circuit diagram. 
OPA501 

POWER OPERATIONAL AMPLIFIER 

Wide power supply range: +10V to +40V 
High output current: ±10A peak 
Available package: Hermetic Metal TO-3 

See Figures 2A and 2B for macromodel circuit diagram. 
OPA511 

POWER OPERATIONAL AMPLIFIER 

Wide power supply range: +10V to +30V 
High output current: +5A peak 
Low distortion class A/B output stage 
Available package: Hermetic Metal TO-3 

See Figures 1C and ID for macromodel circuit diagram. 
OPA512 

POWER OPERATIONAL AMPLIFIER 

Wide power supply range: ±10V to +50V 
High output current: +15A peak 
Low distortion class A/B output stage 
Available package: Hermetic Metal TO-3 

See Figures 1C and ID for macromodel circuit diagram. 



OPA541 

POWER OPERATIONAL AMPLIFIER 

FET input 

Low bias current: 50pA max 
Wide power supply range: +10V to +40V 
High output current: ±10A peak 
Available package: Hermetic Metal TO-3 

See Figures 1C and ID for macromodel circuit diagram. 
OPA602 

OPERATIONAL AMPLIFIER 

FET input 

Low bias current: lpA max 
Fast settling: lus, 0.01% 
Small-signal gain-bandwidth: 6.5MHz 
Slew rate: 35V/(is 

Low input offset voltage: 250[tV max 
Low input offset voltage drift: 2u.V/°C max 
Available packages: Hermetic Metal TO-99, Plastic 8-pin 
DrP, and Plastic 8-pin SOIC. 

See Figures 1C and ID for macromodel circuit diagram. 
OPA603 

(HAS SIMPLIFIED CIRCUIT MODEL ONLY) 

CURRENT-FEEDBACK OPERATIONAL AMPLIFIER 

Wide power supply range: ±4.5 V to +18V 
High output current: ±150mA peak 
Low distortion 

Differential gain: 0.03%, 4.43MHz 

Differential phase: 0.025%, 4.43MHz 
Fast settling: 50ns, 0.1% 

Small-signal gain-bandwidth: 45MHz, Gain = 1 to 100 
High slew rate: 1000V/ns 
Available packages: Plastic 8-pin DIP 

See Figure 3B for macromodel circuit diagram. 
OPA606 

OPERATIONAL AMPLIFIER 

FET input 

Low bias current: lOpA max 
Small-signal gain-bandwidth: 13MHz 
Slew rate: 35V/(is 

Low input offset voltage: 500(iV max 

Input offset voltage drift: 5|iV/°C max 

Available packages: Hermetic Metal TO-99 and Plastic 8- 

pin DIP 

See Figures 1C and ID for macromodel circuit diagram. 



251 



OPA620 

(HAS PSpice® AND SIMPLIFIED CIRCUIT MODEL) 
OPERATIONAL AMPLIFIER 

Low distortion 

Differential gain: 0.05%, 3.58MHz 

Differential phase: 0.05%, 3.58MHz 
Fast settling: 25ns, 0.01% 
Small-signal gain-bandwidth: 200MHz 
Slew rate: 250V/ns 
Low input offset voltage: 100(iV max 
Available packages: Plastic 8-pin DIP and Plastic 8-pin 
SOIC. 

See Figures 2A and 2B for macromodel circuit diagram. 
OPA621 

(HAS PSpice 9 AND SIMPLIFIED CIRCUIT MODEL) 

OPERATIONAL AMPLIFIER 

Stable in gain of 2V/V or higher 
Low distortion 

Differential gain: 0.05%, 3.58MHz 

Differential phase: 0.05%, 3.58MHz 
Fast settling: 25ns, 0.01% 
Small-signal gain-bandwidth: 500MHz 
Slew rate: 500V/(xs 
Low input offset voltage: 100(iV max 
Available packages: Plastic 8-pin DIP and Plastic 8-pin 
SOIC. 

See Figures 2A and 2B for macromodel circuit diagram. 
OPA627 

OPERATIONAL AMPLIFIER 

FET input 

Low bias current: 20pA max 

Low noise: 4.5nV/VHz max, 10kHz 

Low distortion: 0.00003%, 1kHz, Gain = +1V/V 

Fast settling: 550ns, 0.01% 

Small-signal gain-bandwidth: 16MHz 

Slew rate: 55V/us 

Low input offset voltage: lOOuV max 
Low input offset voltage drift: 0.8|iV/°C max 
Available packages: Hermetic Metal TO-99, Plastic 8-pin 
DIP, and Plastic 8-pin SOIC. 

See Figures 1C and ID for macromodel circuit diagram. 
OPA637 

OPERATIONAL AMPLIFIER 

Stable in gain of 5V/V or higher 
FET input 

Low bias current: 20pA max 

Low noise: 4.5nV/VHz max, 10kHz 

Low distortion: 0.00003%, 1kHz, Gain = +1V/V 

Fast settling: 450ns, 0.01% 

Small-signal gain-bandwidth: 80MHz 

Slew rate: 135V/|is 



Low input offset voltage: lOOuV max 
Low Input offset voltage drift: 0.8^V/°C max 
Available packages: Hermetic Metal TO-99, Plastic 8-pin 
DIP, and Plastic 8-pin SOIC. 

See Figures 1C and ID for macromodel circuit diagram. 
OPA1013 

DUAL SINGLE-SUPPLY 
OPERATIONAL AMPLIFIER 

Single power supply operation 

Input common-mode range to negative supply or ground 
Output swings near negative supply or ground 
Low quiescent current: 500(iA max 
Low input offset voltage: 150(iV max 
Input offset voltage drift: 2|iV/°C max 
Input bias-current offset: 0.8nA max 

See figures 3A and 3B for macromodel circuit diagram. 
OPA2107 

DUAL OPERATIONAL AMPLIFIER 

FET input 

Low bias current: 5pA max 
Low noise: 8nV/^Hz max, 10kHz 
Fast settling: 2^s, 0.01% 
Slew rate: 18V/us 

Low input offset voltage: 500fJ.V max 

Input offset voltage drift: 5uV/°C max 

Available packages: Hermetic Metal TO-99, Plastic 8-pin 

DIP, and Plastic 8-pin SOIC. 

See Figures 1C and ID for macromodel circuit diagram. 
OPA2111 

OPERATIONAL AMPLIFIER 

Dual op amp 
FET input 

Low bias current: lpA max 

Low noise: 8nV/VHz max, 10kHz (100% tested) 

Low input offset voltage: 250|iV max 

Low Input offset voltage drift: l\iV/°C max 

Available packages: Hermetic Metal TO-99 

See Figures 1C and ID for macromodel circuit diagram. 

Notes about the macromodel: 

The OPA2111 slew rate is asymmetric with the positive- 
going slope faster than the negative-going slope (4V/ii.s vs 
2V/u.s). Since the PSpice macromodel only allows asymmet- 
ric slew rate in the opposite direction, a conservative sym- 
metrical slew rate of 2V/\is was used in the macromodel. 



Dual op amp 
FET input 

Low bias current: 50pA max 
Wide power supply range: +10V to ±40V 
High output current: ±10A peak 
Available package: Hermetic Metal TO-3 

See Figures 1C and ID for macromodel circuit diagram. 
OPA2604 

DUAL OPERATIONAL AMPLIFIER 

FET input 

Wide power supply range: ±4.5V to ±24V 

Bias current: lOOpA max 

Low noise: 10nV/VHz max, 10kHz 

Low distortion: 0.0003%, 1kHz, Gain = +1V/V 

Fast settling: 2^s, 0.01% 

Slew rate: 25V/H.S 

Small signal gain-bandwidth: 10MHz 

Input offset voltage: 2mV max 

Input offset voltage drift: 5nV/°C typ 

Available packages: Plastic 8-pin DIP and Plastic 8-pin 

SOIC. 

See Figures 1C and ID for macromodel circuit diagram. 

SAMPLE 

MACROMODEL LISTINGS 

STANDARD OPA27 OP AMP MACROMODEL 



* OPA27 OPERATIONAL AMPLIFIER "MACROMODEL" 
SUBCIRCUIT 

* CREATED USING PARTS RELEASE 4.03 ON 09/ 
20/90 AT 16:00 



POSITIVE POWER SUPPLY 
NEGATIVE POWER SUPPLY 
OUTPUT 



NOTICE: THE INFORMATION PROVIDED HEREIN 
IS BELIEVED TO BE RELIABLE; HOWEVER; 
BURR-BROWN ASSUMES NO RESPONSIBILITY FOR 
INACCURACIES OR OMISSIONS. BURR-BROWN 
ASSUMES NO RESPONSIBILITY FOR THE USE OF 
THIS INFORMATION, AND ALL USE OF SUCH 
INFORMATION SHALL BE ENTIRELY AT THE 
USER'S OWN RISK. NO PATENT RIGHTS OR 
LICENSES TO ANY OF THE CIRCUITS DESCRIBED 
HEREIN ARE IMPLIED OR GRANTED TO ANY 
THIRD PARTY. BURR-BROWN DOES NOT AUTHORIZE 
OR WARRANT ANY BURR-BROWN PRODUCT FOR USE 
IN LIFE-SUPPORT DEVICES AND /OR SYSTEMS. 



*SUBCKT OPA27 12 3 4 5 



20.79E-12 

114 .3E-12 

5.713E-12 

DX 

DX 

DX 

DX 

DX 

POLY (2) 
POLY (5) 









CI 


1 1 






C 




-7 
/ 


CEE 


10 


99 


DC 


c 
D 


D J 


DE 


54 


5 




q n 
y U 


Ql 

y l 


DliN 


y^; 


y u 










y y 


u 


r is 


1 


Q Q 

y y 


GA 


6 





GCM 





tz 

D 


IEE 


10 


A 

4 


HLIM 


y 


U 


Ql 


1 1 


z 


Q2 


1 z 


1 

1 


Kz 


D 


Q 

y 


KL1 


•D 
J 


-i i 
ii 


RC2 


■i 


1 z 


RE1 


1 J 


1U 




1 A 


1 u 


REE 


T Pi 
1U 


Q Q 

y y 


ROl 





O 


R02 


7 


99 


RP 


3 


4 


VB 


9 





VC 


3 


53 


VE 


54 


4 


VLIM 


7 


8 


VLP 


91 





VLN 





92 



(3,0) (4,0) .5 .5 
VB VC VE VLP VLN 
10.95E6 -10E6 10E6 10E6 
-10E6 

11 12 4.638E-3 
10 99 2.608E-9 
DC 240.0E-6 
VLIM IK 

13 QX 

14 QX 
100. 0E3 
215.6 
215.6 
5.395E-3 
5.395E-3 
833. 5E3 
35 
35 

10.87E3 
DC 

DC 1.200 
DC 1.200 
DC 
DC 25 
DC 25 

.MODEL DX D (IS=800 . OE-18) 

.MODEL QX NPN(IS=800. OE-18 BF=7.998E3) 

.ENDS 



253 



ENHANCED OPA27 OP AMP MACRO-MODEL 

* OPA27E OPERATIONAL AMPLIFIER "MACROMODEL" 
SUBCIRCUIT 

* "E" IS ENHANCED MODEL 

* CREATED USING PARTS RELEASE 4.03 ON 09/ 
05/90 AT 10:27 



NOTICE: THE INFORMATION PROVIDED HEREIN 
IS BELIEVED TO BE RELIABLE; HOWEVER; 
BURR-BROWN ASSUMES NO RESPONSIBILITY FOR 
INACCURACIES OR OMISSIONS. BURR-BROWN 
ASSUMES NO RESPONSIBILITY FOR THE USE OF 
THIS INFORMATION, AND ALL USE OF SUCH 
INFORMATION SHALL BE ENTIRELY AT THE 
USER'S OWN RISK. NO PATENT RIGHTS OR 
LICENSES TO ANY OF THE CIRCUITS DESCRIBED 
HEREIN ARE IMPLIED OR GRANTED TO ANY 
THIRD PARTY. BURR-BROWN DOES NOT AUTHO- 
RIZE OR WARRANT ANY BURR-BROWN PRODUCT 
FOR USE IN LIFE-SUPPORT DEVICES AND/OR 
SYSTEMS. 



CONNECTIONS: 

* 

* 

* 

* 

* 

*SUBCKT OPA27E 
* 



NON-INVERTING INPUT 
INVERTING INPUT 

POSITIVE POWER SUPPLY 
NEGATIVE POWER SUPPLY 
OUTPUT 
I 

1 2 3 4 5 



CI 


11 


12 


20.79E-12 


C2 


6 


7 


114 .3E-12 


CEE 


10 


99 


5.7131-12 


DC 


5 


53 


DX 


DE 


54 


5 


DX 


DLP 


90 


91 


DX 


DLN 


92 


90 


DX 


DP 


4 


3 


DX 


EGND 


99 





POLY(2) (3,0) (4,0) .5 .5 


FB 


7 


99 


POLY (5) VB VC VE VLP VLN 








10.95E6 -10E6 10E6 10E6 








-10E6 


GA 


6 





11 12 4.638E-3 


GCM 





6 


10 99 2.608E-9 


IEE 


10 


4 


DC 240.0E-6 


HLIM 


90 





VLIM IK 


Ql 


11 


2 


13 QX 


Q2 


12 


1 


14 QX 


R2 


6 


9 


100. 0E3 


RC1 


3 


11 


215.6 


RC2 


3 


12 


215.6 


RE1 


13 


10 


5.395E-3 


RE 2 


14 


10 


5.395E-3 


REE 


10 


99 


833. 5E3 


ROl 


8 


5 


35 


R02 


7 


99 


35 


RP 


3 


4 


10.87E3 











\7"R 


Q 


u 


np n 
u 


vt 




c o 
D ~> 


ut l.ZUU 


VCj 


C A 
D 1 


A 


l.ZUU 


VLIM 


7 


8 


DC 


VLP 


91 





DC 25 


VLN 





92 


DC 25 


* OPA27 * 


E" - 


ENHANCEMENTS 



FQ3 





20 


POLY(l) 


VLIM 1 




DQ1 


20 


21 


DX 






DQ2 


22 


20 


DX 






VQ1 


21 












VQ2 


22 












FQ1 


3 





POLY ( 1 ) 


VQ1 1.5 6E-3 


1 


FQ2 





4 


POLY (1) 


VQ2 1.5 6E-3 


-1 


* QUIESCIENT 


CURRENT 






RQ 


3 


4 


2.5E4 






* DIFF 


INPUT 


CAPACITANCE 




CDIF 


1 


2 


5.0E-12 






* COMMON 


MODE 


INPUT CAPACITANCE 




C1CM 


1 


99 


2.5E-12 






C2CM 


2 


99 


2.5E-12 






* INPUT PROTECTION 






DIN1 


1 


2 


DX 






DIN2 


2 


1 


DX 







.MODEL DX D (IS=800 . 0E-18) 

.MODEL QX NPN(IS=800.0E-18 BF=7.998E3) 

.ENDS 

BURR-BROWN ON LINE 

These files and any updates are also available on Burr- 
Brown's customer service Bulletin Board Service(BBS). 
Call (602) 741-3978 to access the BBS. The BBS operates 
continuously, originating from Burr-Brown's Application 
Engineering department. Contained on the bulletin board 
are new product announcements, application notes, software 
utilities and a technical support message center. Users of the 
system can also access on line databases to find cross- 
references to competitor's components, find pricing for all 
Burr-Brown products and order application notes, product 
data sheets or article reprints. 

File transfers are supported by XMODEM, Kermit, ASCII 
and Sealink protocols. Communication settings are 300/ 
1200/2400 baud, 8-N-l. 



The information provided herein is believed to be reliable; however, BURR- 
BROWN assumes no responsibility for inaccuracies or omissions. BURR- 
BROWN assumes no responsibility for the use of this information, and all use of 
such information shall be entirely at the user's own risk. Prices and specifications 
are subject to change without notice. No patent rights or licenses to any of the 
circuits described herein are implied or granted to any third party. BURR- 
BROWN does not authorize or warrant any BURR-BROWN product for use in life 
support devices and/or systems. 



SELECTED SUBJECTS INDEX 



Active Filters - 133,139,143,151,159 
Bridge Amplifier - 27 
Current Sources - 3,83,121 
Electrical Properties - 1 
Frequency Compensation - 35 
Heat Sinking - 227,229 

Instrumentation Amplifier Macromodels - 237 

Macromodels - 237 

Materials - 1 

Mounting TO-3 - 229 

OP Amp Macromodels - 237 

Photodiode Amplifier - 28,29,30 

Spice Macromodels - 237 

Thermal Properties - 1 

Voltage References - 123,125,127,129,131 

MODEL INDEX 

ADC603 - 173 

ADS7800 -175,176 

DAC7541 -126 

HPR117 -87,89,117,118,119 

INA1 05 - 23,24,26,27,61 ,62,63,65,67,1 05,1 06,1 07,1 27,1 29,1 31 ,1 32,1 82 

INA106 -52,53,73,74,77,131 

INA110 -18 

INA117 - 27,49,50,51,55,56,61,62,63,65,79,80,81,82,108 
ISO120/121 -106,108,109,113 

IS0122 - 87,89,105,106,107,115,117,118,119 

MPY634 - 45 

OPA1013 - 10,23,97,99,100,101,102,103,106,107 

OPA111 -8,38,40,44,121 

OPA121 -20,21 

OPA128 - 7,39,77 

OPA177 - 56,73,74,75,86,136,157,171,176 

OPA2107 - 34,52,53,74,77,136,157,171 

OPA2111 -42,46 

OPA2604 -136,145,148 

OPA27 - 49,50,55,56,123,124,125,128,130,136,157,171 

OPA404 -73,136,157 

OPA445 - 75 

OPA602 - 7,9,10,15,18,19,21,22,23,29,30,51,52,53,109,114, 

115,136,157,171,178,180 

OPA603 - 33 

OPA620 - 136,157,173 

OPA627 - 33,136,140,145,157,171 

OPA633 - 24 

RCV420 - 28,57,69,70,87,89 

REF101 -128 

REF102 - 8,121,123,124,125,126,127,128,129,130,131,132 

REF200 - 4,5,6,7,9,10,11,12,13,14,15,16,17,18,19,20,21, 

22,23,73,74,75,77,97,99,1 00,1 01 ,1 02,1 03,1 07,1 1 9 

UAF42 - 159,163,164,165,166,168,169,171 

VFC110 -177 

VFC121 - 177 

VFC320 -177,178,180 

XTR1 01 - 25,87,88,90,91 ,92,93 

XTR103 - 87,94 

XTR104 - 87,95 

XTR110 -25